Industrial Technology Research Institute

Ra-Min Tain

Shyi-Ching Liau

Ming-Ji Dai

John H Lau

Ming-Che Hsieh

Wei-Chung Lo

Shu-Jung Yang

Yung-Yu Hsu

Chun-Kai Liu

Tzong-Che Ho

Wei-Kuo Han

Rong-Shen Lee

Chi-Shih Chang

Yu-Lin Chao

Wei Yu Li

Chih-Yuan Cheng

Yao-Shun Chen

Rong-Chang Feng

Chih-Kuang Yu

Shou-Lung Chen

Heng-Chieh Chien

Shan-Pu Yu

Wen-Yang Peng

Ji-Cheng Lin

Syh-Yuh Cheng

Yun-Tien Chen

Jr-Yuan Jeng

Rong-Chang Fang

Chin-Lung Chen

Shu-Ming Chang

Min-Lin Lee

Shyh-Shyuan Sheu

Ming-Te Lin

Shih-Hsien Wu

Chih-Sheng Lin

Chun-Chuan Lin

Je-Ping Hu

Sheng-Tsai Wu

Kuang-Yu Tai

I-Nan Lin

Li-Cheng Shen

Chien-Cheng Yang

Sheng-Liang Li

Kung-Hsia Wang

Ping-Hsin Hsia

Hsien-Chang Lee

Chao-Hsien Chang

Chung-Yen Hsu

Chen-Hung Chew

Chih-Yuah Cheng

Shyl-Ching Liau

Hei-Tong Ching

Yon-Hua Tzeng

Jui-Feng Hung

A wafer stack includes: a first wafer having a first substrate and a first device layer having therein at least a chip; a second wafer having a second substrate disposed above the first wafer; and at least a first metal post existing in the first device layer, and arranged between the first and the second substrates, without being electrically connected to the chip.

Wafer-to-wafer stack with supporting post

An electronic device having a stacked structure is provided. The electronic device includes a first electronic layer, a second electronic layer disposed on the first electronic layer, and at least a post. The first electronic layer has a first interface, and including a first substrate and a first device layer disposed on the first substrate. The first interface is located between the first substrate and the first device layer, and the first device layer has a surface opposite to the first interface. The post is arranged in the first device layer, and extending from the first interface to the surface of the first device layer.

Wafer-to-wafer stack with supporting pedestal

A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test.

Fabricating method of semiconductor device

A semiconductor device including a silicon substrate, a plurality of silicon nanowire clusters, a first circuit layer and a second circuit layer. The silicon substrate has a first surface, a second surface opposite to the first surface and a plurality of through holes. The silicon nanowire clusters are disposed in the through holes of the silicon substrate, respectively. The first circuit layer is disposed on the first surface and connected to the silicon nanowire clusters. The second circuit layer is disposed on the second surface and connected to the silicon nanowire clusters.

Semiconductor device

A heat dissipation structure for an electronic device includes a body having a first surface and a second surface opposite to the first surface. A silicon-containing insulating layer is disposed on the first surface of the body. A chemical vapor deposition (CVD) diamond film is disposed on the silicon-containing insulating layer. A first conductive pattern layer is disposed on the silicon-containing insulating layer, wherein the first conductive pattern layer is enclosed by and spaced apart from the CVD diamond film. A method for fabricating a heat dissipation structure for an electronic device and an electronic package having the heat dissipation structure are also disclosed.

Heat dissipation structure for electronic device and fabrication method thereof

Package structures for integrating thermoelectric components with stacking chips are presented. The package structures include a chip with a pair of conductive through vias. Conductive elements are disposed one side of the chip contacting the pair of conductive through vias. Thermoelectric components are disposed on the other side of the chip, wherein the thermoelectric component includes a first type conductive thermoelectric element and a second type conductive thermoelectric element respectively corresponding to and electrically connecting to the pair of conductive through vias. A substrate is disposed on the thermoelectric component, wherein the thermoelectric component, the pair of conductive through vias and the conductive element form a thermoelectric current path. Therefore, heat generated from the chip is transferred outward through a thermoelectric path formed from the thermoelectric components, the conductive through vias and the conductive elements.

Package structures for integrating thermoelectric components with stacking chips

An electronic device packaging structure is provided. The semiconductor device includes a semiconductor base, an emitter, a collector, and a gate. The emitter and the gate are disposed on a first surface of the semiconductor base. The collector is disposed on a second surface of the semiconductor base. A first passivation layer is located on the first surface of the semiconductor base surrounding the gate. A first conductive pad is disposed on the first passivation layer. A second conductive pad is disposed on the collector on the second surface. At least one conductive through via structure penetrates the first passivation layer, the first and second surfaces of the semiconductor base, and the collector to electrically connect the first and second conductive pads.

Electronic device packaging structure

A chip stacking structure including a carrier, a first redistribution layer, a second redistribution layer, at least one first chip, at least one second chip, and at least one conductor is provided. The carrier has a first surface and a second surface opposite to each other. The carrier has at least one through hole. The first and second redistribution layers are disposed on the first and second surfaces of the carrier, respectively. The first and second chips are disposed on the first and second surfaces of the carrier and electrically connected with the first and second redistribution layers, respectively. The conductor is disposed on one of the first and second chips. The conductor is disposed in the through hole. The first and second chips are electrically connected by the conductor. A gap is formed between the conductor and an inner wall of the carrier which surrounds the through hole.

Chip stacking structure and fabricating method of the chip stacking structure

A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface. The first heater comprises a plurality of first switches connected in series to generate heat.

Measuring apparatus that includes a chip with a through silicon via, a heater having plural switches, and a stress sensor

A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface.

Measuring apparatus that includes a chip having a through silicon via, a heater, and a stress sensor

By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased.

Filled through-silicon via with conductive composite material

A heat-pipe electric power generating device includes a heat pipe having an evaporating end and a condensing end, a non-magnetic shell connected to the condensing end, a generator stator coil disposed at the outer of the non-magnetic shell, a turbine disposed in the heat pipe, a driving axle connected to the turbine and extended into the non-magnetic shell, and a magnetic element disposed at the driving axle and located in the non-magnetic shell. A vapor flow flowing to the condensing end is generated at the evaporating end. The vapor flow drives the turbine to move the magnetic element, such that the generator stator coil generates an induced current. In addition, a hydrogen/oxygen gas generating apparatus and an internal combustion engine system having the heat-pipe electric power generating device are also provided.

Heat-pipe electric power generating device and hydrogen/oxygen gas generating apparatus and internal combustion engine system having the same

A heat-pipe electric power generating device including a fan disposed between an evaporating end and a condensing end of a heat-pipe is provided. A magnetic substance is disposed on the fan to form a magnetic field. A stator coil of a generator is disposed at the outer of the heat-pipe, which is corresponding to the position of the fan. An induced current is generated by the stator coil of the generator when the magnetic substance spins. Since the heat-pipe is made of copper, and the magnetic field is not shielded by copper, a current is induced when a relative motion between the magnetic substance on the fan and the stator coil of the generator at the outer of the heat-pipe is generated. Further, the heat-pipe electric power generating device can be applied on a hydrogen/oxygen gas generating apparatus and an internal combustion engine system of a motor vehicle.

A light-emitting device may include a heat-dissipating base, a light-emitting unit, a housing, and a first conductive contact and a second conductive contact. The heat-dissipating base has a top portion and a bottom portion. The bottom portion of the heat-dissipating base may include an exposed heat-dissipation surface. The light-emitting unit is over the top portion of the heat-dissipating base and is arranged to provide heat conductivity at least from the light-emitting unit to the heat-dissipating base. The light-emitting unit may include at least one light-emitting diode for emitting light and a first electrode and a second electrode. Heat may be generated as the light-emitting diode emits light, and the at least one light-emitting diode may have power input terminals for receiving power input to the at least one light-emitting diode. The power input may include one of an alternating-current input and a direct-current input. The first electrode and the second electrode are electrically coupled with the input terminals of the at least one light-emitting diode. The housing encloses at least a portion of the light emitting unit and covers the top portion of the heat-dissipating base. The first conductive contact and the second conductive contact are near or below a portion of the heat-dissipating base and are configured to receive external power supply. The first conductive contact may be electrically coupled with the first electrode, and the second conductive contact may be electrically coupled with the second electrode.

Light emitting devices having heat-dissipating surface

Fabricating method and testing method of semiconductor device and mechanical integrity testing apparatus

Growing community of inventors

Taipei County, Taiwan

Ra-Min Tain