Ltx Corporation

Ltx-credence Corporation

R Warren Necoechea

Mark E Deome

William Robert Creek

Christopher Joel Hannaford

Solomon Max

Timothy Alton

Timothy Burnett

Dave Hollinbeck

Fengming Zhang

Harry Hou

A method for identifying and reducing spurious frequency components is provided. A method in accordance with at least one embodiment of the present disclosure may include generating a digital sinusoidal waveform at a direct digital synthesizer (DDS) and receiving the digital sinusoidal waveform at an audio digital-to-analog converter. The method may further include converting the digital sinusoidal waveform to an analog sinusoidal waveform containing spurious frequency components, combining the analog sinusoidal waveform with an analog distortion correction waveform to generate a composite output waveform and receiving the composite output waveform at notch filter circuitry. The method may also include filtering the composite output waveform to generate a filtered composite output waveform and amplifying a difference between the filtered composite output waveform and a signal from a circuit-under-test (CUT) to generate an amplified analog signal. The method may also include converting the amplified analog signal to an amplified digital signal. Of course, additional implementations are also within the scope of the present disclosure.

Method and apparatus for identifying and reducing spurious frequency components

A filter includes at least a pin diode, an inductive element, and a varactor diode coupled as a resonant circuit. The filter injects data dependent jitter into a digital data signal with a given data rate for testing a transceiver.

Testing a transceiver

An apparatus to receive a response signal sent from a device under test. The apparatus includes pin electronics to identify a response signal contained in a composite signal. The composite signal is a composite, or sum, of the response signal and a test signal. The pin electronics has a driver to send the test signal to the device under test, and a receiver to receive the composite signal and to separate the response signal from the composite signal.

Separating device response signals from composite signals

A method is described that decompresses at least a section of a first test pattern within a first decompression engine while simultaneously decompressing at least a section of a second test pattern within a second decompression engine. The first test pattern is to be applied to a first device under test (DUT) connection. The second test pattern is to be applied to a second DUT connection.

Method and apparatus for distributed test pattern decompression

A method and apparatus for generating timing markers in an automatic electrical test system. Timing parameters are synchronized by an external period start signal corresponding to a centrally generated external period and an internal period start signal generated locally for each input/output pin. The timing parameters comprise T1 counter and vernier values, T2 counter and vernier values, and period-minus-T1 counter and period vernier values.

Timing generation in an automatic electrical test system

A phase shift vernier for providing an output signal with continuously variable delay based on an input phase delay is disclosed. The apparatus comprises delay value means, a ring oscillator, a multiplexer, a DAC, and a signal combiner. The delay value means is adapted for receiving an input phase delay value, indicating the amount of delay for an output signal. The ring oscillator is adapted for circulating an oscillating signal through multiple differential stages to generate multiple quadrature signals. The oscillating signal has a predetermined frequency and each of the differential stages is connected in series. Each of the stages delays its inputs by a predetermined amount to generate its differential outputs from each stage. The multiplexor is coupled to the ring oscillator and to the delay value means to receive the quadrature signals from the ring oscillator. The multiplexor selects first and second quadrature signals from the ring oscillator in response to the input phase delay from the delay value means. The first and second quadrature signals are offset by 90 degrees. The DAC is coupled to the multiplexor and to the delay value means to generate a first and second currents based on the input phase delay from the delay value means. The signal combined is coupled to the DAC and to the multiplexor for generating the output signal phase-shifted by the input phase delay. The signal combiner multiplies the first and second quadrature signals with the first and second currents to generate third and fourth quadrature signals, respectively. The signal combiner further combines the third and fourth quadrature signals to generate the output signal.

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Scotts Valley, CA, United States of America

R Warren Necoechea