Intel Corporation

R Scott Tetrick

Dale J Juenemann

Oscar P Pinto

Glenn J Hinton

Steven E Wells

Amber D Huffman

Jeanna N Matthews

Brian Dees

Robert J Brennan

Raghu Murthi

Dale Jeunemann

Jordan Howes

In some embodiments, a non-volatile cache memory may include a segmented non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the segmented non-volatile cache memory, wherein the controller is configured to control utilization of the segmented non-volatile cache memory. The segmented non-volatile cache memory may include a file cache segment, the file cache segment to store complete files in accordance with a file cache policy, and a block cache segment, the block cache segment to store one or more blocks of one or more files in accordance with a block cache policy, wherein the block cache policy is different from the file cache policy.

Apparatus and method for segmented cache utilization

In some embodiments, an electronic system may include a cache located between a mass storage and a system memory, and code stored on the electronic system to prevent storage of stream data in the cache and to send the stream data directly between the system memory and the mass storage based on a comparison of first metadata of a first request for first information and pre-boot stream information stored in a previous boot context. Other embodiments are disclosed and claimed.

Apparatus and method for cache utilization

In some embodiments, a processor-based system includes a processor, a system memory coupled to the processor, a mass storage device, a cache memory located between the system memory and the mass storage device, and code stored on the processor-based system to cause the processor-based system to utilize the cache memory. The code may be configured to cause the processor-based system to preferentially use only a selected size of the cache memory to store cache entries having less than or equal to a selected number of cache hits. Other embodiments are disclosed and claimed.

Apparatus and method for low touch cache management

In some embodiments, a non-volatile cache memory may include a segmented non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the segmented non-volatile cache memory, wherein the controller is configured to control utilization of the segmented non-volatile cache memory. The segmented non-volatile cache memory may include a file cache segment, the file cache segment to store complete files in accordance with a file cache policy, and a block cache segment, the block cache segment to store one or more blocks of one or more files in accordance with a block cache policy, wherein the block cache policy is different from the file cache policy. The controller may be configured to utilize the file cache segment in accordance with information related to the block cache segment and to utilize the block cache segment in accordance with information related to the file cache segment. Other embodiments are disclosed and claimed.

In some embodiments, a non-volatile cache memory may include a multi-level non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the multi-level non-volatile cache memory, wherein the controller is configured to control utilization of the multi-level non-volatile cache memory. Other embodiments are disclosed and claimed.

Apparatus and method for multi-level cache utilization

Disclosed is a method for handling conflicting deadlines by a disk drive. The method comprises: receiving a plurality of requests from a plurality of applications for accessing the disk drive; determining a plurality of service times for the plurality of requests; serving a first request of the plurality of request prior to an actual schedule when a deadline for serving the first request and a deadline for serving a subsequent request of the plurality of requests cannot be simultaneously met by the disk drive; and serving the subsequent request after the first request is served by the disk drive.

Disk drive for handling conflicting deadlines and methods thereof

Methods and apparatuses for identifying types of data streams and communicating stream information to improve performance of data storage devices are disclosed. Method embodiments generally comprise identifying one or more isochronous requests among a plurality of requests which may be issued to a data storage device, assigning a completion deadline an isochronous request, and communicating the isochronous request and completion deadline information to the data storage device. Apparatus embodiments generally comprise a request identifier to identify an isochronous request, a logic module to assign a completion deadline to the isochronous request, and a communication module to communicate the isochronous request and the completion deadline to a data storage device. Alternative apparatus embodiments may include a monitor module to monitor a system process operating in the system and determine if the system process issues isochronous requests. Various embodiments may process asynchronous requests, including prioritized asynchronous requests, with the isochronous requests.

Data storage device performance optimization methods and apparatuses

A data caching method comprising monitoring read and write requests submitted for accessing target data in a first data block on a storage medium; identifying a sequence of access requests for target data as a first stream; and determining whether the first stream is suitable for direct disk access based on inter-arrival times of the read or write requests in the stream.

Using inter-arrival times of data requests to cache data in a computing environment

A memory card detection method comprising detecting insertion of a memory card into a device's card slot; creating a memory card construct in a non-volatile memory storage; copying data from the memory card to the memory card construct; and informing the device that a new memory card has been inserted and may be accessed from the non-volatile memory storage.

Loading data from a memory card

A method and apparatus for a multi-ranked memory protocol. In some embodiments an apparatus may include a memory controller (MC), and a plurality of ranked dynamic random access memory (DRAM) devices interfaced with the MC, wherein timing and initiation operations between the MC and the plurality of ranked DRAM devices and between the plurality of ranked DRAM devices is controlled by the MC. In some embodiments, a method may include addressing a request to one of a plurality of ranked DRAM devices, sending the request from a MC interfaced with the plurality of ranked DRAM devices, and propagating the request from the MC through the plurality of ranked DRAM devices to the addressed ranked DRAM device MC, wherein the requests includes data associated therewith.

System and method to increase DRAM parallelism

A method for synchronizing testing of shared memory contained in a multi-processor computer system after reset. The method involves the steps of performing a wake-up procedure by a bootstrap processor on the other processors. Thus, the other processors can assist in testing the shared memory. Next, respective portions of the shared memory are allocated to each of the processors. Finally, upon completion of testing of its respective portion of the shared memory, each processor sets its unique storage unit synchronizing the processors at completion.

System and method for synchronizing multiple processors during power-on

A power down control mechanism for multiprocessor computer systems. A power down register is maintained for providing a power down control signal to the multiple processing units in the multiprocessing system. Individual processing units can be selectively onlined or offlined as needed. In addition, during system initialization, the power down mechanism of the present invention can be used for onlining additional processors and also used for preventing faulty processors from attempting to become the system's boot system processor.

Microprocessor power control in a multiprocessor computer system

In a shared memory computer system, processing nodes are coupled together by way of cluster bridges. A cluster bridge operating according to the present invention intercepts a global access transaction request issued from a processing node and issues a transaction deferral to indicate that the request will be serviced out-of-order. A map of global addresses which correspond to fixed addresses at the node from which the access request was issued is maintained by the cluster bridge. If the address of the global access transaction request corresponds to a fixed address local to the requesting node, the address is translated at cluster bridge and accessed at the local node in order to complete the deferred request.

Use of deferred bus access for address translation in a shared memory

An arbiter for the local bus of a computer system. The system contains a bridge and a plurality of agent devices that are all connected to a local bus. The bridge links the local system to a remote system. The bridge and one of the agents (DEFER agent) within the local system can communicate in correspondence with the Non-uniform memory access(NUMA) standard. The local system also contains an agent (DEFERless agent) that does not comply with the NUMA standard. The arbiter provides access to the local bus in response to a request from one of the agents on a corresponding bus access signal line. If the DEFERless agent generates a remote access request and the bridge cannot immediately service the request, the bridge provides a negative acknowledge to the agent and disables the DEFERless agent bus access signal so that the DEFERless agent cannot control the local bus. The remaining agents can access the local bus even when the DEFERless agent is waiting for service from the bridge. The bridge enables the bus access signal of the DEFERless agent when the bridge can serve a remote access request.

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Portland, OR, United States of America

R Scott Tetrick