Intel Corporation

Real 3-d

R Scott Hartog

Michael Mantor

Thomas A Piazza

Aditya Sreenivas

Michael Andrew Mang

Ralph Clayton Taylor

Kam Leung

Brian D Rauchfuss

John A Carey

Jeffrey D Potter

Sajjad A Zaidi

A rasterizer comprised of a bounding box calculator, a plane converter, a windower, and incrementers. For each polygon to be processed, a bounding box calculation is performed which determines the display screen area, in spans, that totally encloses the polygon and passes the data to the plane converter. The plane converter also receives as input attribute values for each vertex of the polygon. The plane converter computes planar coefficients for each attribute of the polygon, for each of the edges of the polygon. The plane converter unit computes the start pixel center location at a start span and a starting coefficient value at that pixel center. The computed coefficients also include the rate of change or gradient, for each polygon attribute in the x and y directions, respectively. The plane converter also computes line coefficients for each of the edges of the polygon. Line equation values are passed through to the windower where further calculations allow the windower to determine which spans are either covered or intersected by the polygon. The incrementers receive the span coverage data from the windower in addition to receiving planar coefficient values from the plane converter. The incrementers utilize the data from both the windower and plane converter to walk or traverse the polygon in those intersected spans, pixel by pixel. As the incrementer visits each pixel, vertex attribute values are interpolated to each pixel.

Method and apparatus to efficiently interpolate polygon attributes in

A pipeline apparatus for processing 3D graphics data will be described. The pipeline apparatus includes a first request memory to fetch information corresponding to a texture operand. A second request memory fetches information responding to a color operand and Z operand. A control circuit coordinates data flow from the first request memory and the second request memory into a memory channel by preventing the number of requests from the first request memory from exceeding by a predetermined number, the number of requests from the second request memory. By properly coordinating the data flow, deadlock of a data fetching pipeline is avoided.

Data skew management of multiple 3-D graphic operand requests

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Orlando, FL, United States of America

R Scott Hartog