Cray Incorporated

Smithills Multimedia Systems, Inc.

R Paul Dixon

David R Resnick

Van L Snyder

Gerald A Schwoerer

Roger A Bethard

Michael Higgins

Kelly J Marquardt

Michael L Steinberger

Alan M Grossmeier

Thanos Mentzelopoulos

A memory controller and method that provide a read-refresh (also called 'distributed-refresh') mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

Apparatus and method for memory bit-swapping-within-address-range circuit

Apparatus and method for memory with bit swapping on the fly and testing

A data processor memory system that combines in a single memory array, a plurality of first-in-first-out (FIFO) buffer memories and a dual-port random access read-write memory (RAM). The memory array is divided into one region for the FIFO buffers and another region for the RAM memory. The memory system reads and writes data to the RAM region independently of the FIFO buffer region. The system enables access to the RAM memory by signals addressed to address fields within the RAM region, and enables access to the FIFO buffer memories by signals addressed to address fields within the FIFO region. The system writes data to each of the FIFO buffer memories utilizing an associated write pointer, and increments each write pointer when data is written to its associated FIFO buffer memory. The system reads data from each of the FIFO buffer memories utilizing an associated read pointer, and increments the read pointer when data is read from its associated FIFO buffer memory. The write pointers and the read pointers roll-over to a first address in their associated FIFO buffers when each pointer reaches the top of addressable memory in its associated FIFO buffer memory.

Combination dual-port random access memory and multiple

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Carrollton, TX, United States of America

R Paul Dixon