Burr-brown Corporation

Texas Instruments Corporation

Texas Instruments Tucson Corporation

R Mark Stitt, Ii

Rodney T Burt

Walter Baker Meinel

Timothy V Kalthoff

David A Heisley

Edward Mullins

Tony Ray Larson

Anthony D Wang

Thomas A Somerville

Johnnie F Molina

David M Jones

Jeffrey B Parfenchuck

Larry D Hobson

A method and apparatus for auto-calibrating an electronic device without interrupting normal operation of the device. An electronic device configured as a high voltage difference amplifier is disclosed having a calibration circuit which couples a calibration excitation signal to a common-mode signal path of the difference amplifier. The difference amplifier includes a variable transfer function circuit which may be used to adjust the common-mode rejection of the difference amplifier. The calibration excitation signal may be a random, pseudo-random, out-of-band, or other frequency shaped signal generated in reference to a clock signal. A calibration error signal is detected from an output signal. The variable transfer function circuit can be adjusted in response to the detected error signal to reduce the calibration error signal. As a result, common-mode rejection errors of the difference amplifier may be reduced while the difference amplifier is coupled to an input signal source.

Method and apparatus for calibration of an electronic device

A temperature-compensated monolithic logarithmic amplifier includes a logarithmic amplifier cell ( ) configured to produce a logarithmic voltage signal (V ) representative of a difference between a first voltage (V ) developed across a first PN junction device (D ) in response to an input signal (I ) and a second voltage (V ) developed across a second PN junction device (D ) in response to a reference signal (I ) and an output circuit ( ) including an output amplifier ( ), a temperature-dependent first resistive element (R ) having a positive temperature coefficient, and a second resistive element (R ). The output circuit ( ) produces a temperature-compensated output signal (V ) in response to the logarithmic voltage signal (V ). The first resistive element (R ) is composed of conductive aluminum or aluminum alloy interconnection metallization that also is utilized as interconnection metallization throughout the monolithic logarithmic amplifier.

Method and circuit for compensating VT induced drift in monolithic logarithmic amplifier

Low temperature coefficient leadframe

A low drop out voltage regulator includes an error amplifier (,) having a first input coupled to a first reference voltage (V,), a second input receiving a feedback signal, and an output (,) producing an output signal (V,). An output transistor (,) has a gate, a drain coupled to an unregulated input voltage (V,), and a source coupled to produce a regulated output voltage (V,) on an output conductor (,). A feedback circuit (,) is coupled between the output conductor (,) and a reference voltage (GND) to produce the feedback signal. A capacitor (,) is coupled between the output (,) of the error amplifier and the gate (,) of the output transistor (,). A servo amplifier (,) has a first input coupled to a second reference voltage (VV,), a second input coupled to the output (,) of the error amplifier. A low current charge pump circuit (,B) supplies an output current into a supply voltage terminal of the servo amplifier. A variable reference voltage circuit (,) produces the second reference voltage (VV,) so as to increase the dynamic range of the voltage regulator. An output current sensing circuit (,) operates to produce a control signal (,) representative of the drain current of the output transistor (,), the variable reference voltage circuit (,) having an input coupled to receive the control signal (,).

Low dropout voltage regulator circuit including gate offset servo circuit powered by charge pump

An integrated circuit photodetector includes a transimpedance amplifier including a differential amplifier stage with PNP emitter-coupled transistors and a PNP input transistor which are biased only by base currents of the emitter-coupled transistors, to achieve low input bias current. Low noise operation is achieved by bypass capacitors coupled between the bases and emitters of the input transistors, respectively. A constant current source supplies a current which develops a small pedestal voltage across a resistor to bias the non-inverting input of the transimpedance amplifier so as to avoid nonlinear amplification of low level light signals. A positively biased N-type guard tub surrounds the photodetector, which is formed in a junction-isolated N region on a P substrate, to collect electrons generated in the substrate by deep-penetrating IR light to prevent them from causing amplification errors. In one embodiment, a feedback network includes a resistor connected between the output of a buffer driven by the transimpedance amplifier and an inverting input thereof, and a capacitor connected between the output and inverting input of the transimpedance amplifier to provide low noise, fast settling operation.

Integrated photodiode/transimpedance amplifier

A planar transformer assembly includes an insulative layer, a first spiral winding thereon circumscribing a magnetic flux path, a second spiral winding thereon in non-overlapping relation to the first spiral winding circumscribing the magnetic flux path, and a ferrite core assembly including first and second core sections defining a shallow gap or passage within which the spiral windings are disposed. In one embodiment, a plurality of laminated insulative layers are provided with a primary winding including a plurality of series-connected spiral subwindings and a non-overlapping secondary winding formed on the various insulative layers. The non-overlapping structure and the order of the various windings minimize electric field gradients and thereby minimize electric field coupled noise currents.

Planar transformer assembly including non-overlapping primary and

A planar transformer includes a multilayer printed circuit board having a plurality of spiral windings formed by metalization on various surfaces of the printed circuit board. A ferrite core assembly includes first and second core sections disposed on opposite sides of the printed circuit board and completely confining the conductors of the spiral windings. Each core section includes a thin, flat plate. The two flat plates are integral with or abut thin post sections that are thick enough to allow the printed circuit board to be accommodated between the first and second core sections. In one embodiment of the invention, the planar transformer is incorporated on the printed circuit board with other circuitry to form a low noise battery charger which is encapsulated in a male power connector.

Hybrid integrated circuit planar transformer

A circuit for reducing input offset error and improving gain switching speed in a programmable gain amplifier includes a level shifting buffer that senses a signal on a common mode conductor in a differential input stage of an operational amplifier, and shifts the level of that signal up to the level corresponding to a level of an input signal applied to a non-inverting input of the operational amplifier. If a gain select signal is at a first logic level, the voltage produced by the buffer is applied to a gate electrode of one of a plurality of gain switching JFETs coupling a gain network to the inverting input of the operational amplifier, turning that JFET on. If the gain select signal is at a second logic level, the output of the buffer is isolated from the gain switching JFET and a turn off voltage is applied to the gate of the gain switching JFET.

Programmable gain amplifier circuitry and method for biasing JFET gain

Circuitry for reducing harmonic distortion in an amplifier includes a first transistor having a first non-linear collector-to-substrate capacitance, a first load device coupled to a collector of the first transistor, a first current source coupled to an emitter of the first transistor, a first conductor conducting an input voltage coupled to a base of the first transistor, and a second conductor coupled to the first load device and conducting an output voltage of the amplifier. The first transistor produces a first non-linear current in the first non-linear collector-to-substrate capacitance in response to the input voltage. A second transistor has a second non-linear collector-to-substrate capacitance. A second current source is coupled to an emitter of the second transistor. The first conductor is coupled to apply the input voltage to a base of the second transistor. The second transistor produces a second non-linear current in the second non-linear collector-to-substrate capacitance in response to the input voltage. A current mirror receives a collector current of the second transistor. The current mirror produces in the second conductor a correction signal substantially equal and opposite to the first non-linear current.

Circuit technique for cancelling non-linear capacitor-induced harmonic

A common-base, source-driven differential amplifier achieves both high speed operation and low noise operation by providing an input stage including a pair of source follower JFETs that drive emitters of a pair of NPN input transistors having their bases connected together and to a bias circuit. The collectors of the NPN transistors each are connected to a corresponding load device and to a corresponding input of an output amplifier stage. The bias circuit includes a current source and a pair of diode-connected NPN transistors having their bases and collectors connected to the current source and to the bases of the input transistors. The emitters of the diode-connected NPN transistors are connected to sources of a second pair of source follower JFETs, the gates of which are connected to the input terminals.

Common-base, source-driven differential amplifier

A wideband integrated circuit amplifier includes a pair of current mirror circuits sensing emitter currents of NPN and PNP transistors in the amplifier output stage. A pair of current mirror circuits divide the emitter currents, respectively, by a factor of 20. The current mirror output currents are summed, current splitter directs approximately 1/20 of the summed mirror currents through a transistor, the collector of which is coupled to the gate electrode of a field effect input transistor of a bias control circuit, to produce a scaled down feedback current. A high impedance current source is connected to the collector of the transistor. The bias circuit adjusts the DC bias voltage applied between the base electrodes of the transistors to cause the scaled down feedback current to equal the constant current. A very small compensation capacitor produces a low frequency pole that prevents the bias circuit from interfering with high frequency performance characteristics of a wide band amplifier.

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Tucson, AZ, United States of America

R Mark Stitt, Ii