Massachusetts Institute of Technology

The Charles Stark Draper Laboratory, Inc.

Baylor College of Medicine

Houston Advanced Research Center

R Allen Murphy

Dennis D Rathman

Carl O Bozler

Gary D Alley

William T Lindley

Wendell Eugene Rhine

Daniel J Ehrlich

Mark Alexander Hollis

Barry E Burke

William L Robbins

Michael E Hogan

Bernard B Kosicki

William D Goodhue

John S Haggerty

Richard Hart Mathews

George B Kenney

Rajender S Varma

Mitch D Eggers

Julia Sigalovsky

Annamarie Lightfoot

Robert P Berger

Robert K Reich

Chang-Lee Chen

Bernard Kosicji

Michael Rose

Richard Osgood

A large format imager includes an array of pixels for converting electromagnetic radiation into electrical signals and a trigger to from an optical pulse so as to trigger the pixels to generate an integration period. Each pixel includes a photodiode to convert light intensity of high-frequency radiation into an electrical charge, a reset switch to reset the photodiode, circuitry to enable sampling of the electrical charge produced by the photodiode, a photoswitch to convert an optical trigger pulse, received from the trigger, into an electrical signal, an inverter to produce a control signal corresponding to the electrical signal produced by the photoswitch, and control circuitry to locally generate integration control signals. The integration control signals control a start of an integration period for the photodiode, duration of the integration period for the photodiode, and the sampling of the electrical charge produced by the photodiode. The large format imager may also include a trigger for producing an electrical pulse so as to trigger the pixels to generate an integration period and tree type electrical distribution system for propagating the electrical pulse to all the pixels, wherein each pixel includes a global repeater circuit to propagate a first edge of said electrical pulse along said tree type electrical distribution system and a local repeater circuit to provide a local array of pixels with the first edge of the electrical pulse.

Method and system for distribution of an exposure control signal for focal plane arrays

A method and apparatus are disclosed for identifying molecular structures within a sample substance using a monolithic array of test sites formed on a substrate upon which the sample substance is applied. Each test site includes probes formed therein to bond with a predetermined target molecular structure or structures. A signal is applied to the test sites and certain electrical, mechanical and/or optical properties of the test sites are detected to determine which probes have bonded to an associated target molecular structure.

Optical and electrical methods and apparatus for molecule detection

An electronic device package is provided, consisting of reaction bonded silicon nitride structural and dielectric components and conductor, resistor, and capacitor elements positioned with the package structural components. The package consists of a ceramic package base characterized by a dielectric constant less than 6, of reaction bonded silicon nitride, or a heat spreader material. An electrical conductor is positioned on, embedded in, or attached to the package base for making electrical contact to an electronic device supported on the base and in preferred embodiments, a resistor is attached to the package base. The invention also provides package sidewalls connected to the package base, preferably of reaction bonded silicon nitride, and at least one electrical conductor extending to an outside surface of the package sidewalls for making electrical contact to an electronic device supported by the package base. The reaction formed electronic device packages of the invention provide the ability to support high device signal frequencies, high device operational temperatures, and high environmental temperatures, due to the characteristics of the package materials. The reaction formed electronic device packages of the invention may be produced with a nitriding process during which the overall package structure exhibits minimal shrinkage. As a result, the reaction formed electronic device packages of the invention may be shaped to finished dimensions before the nitriding process with complicated and tight-tolerance geometries of package structural, conducting, resistive, and capacitive components.

Net-shape ceramic processing for electronic devices and packages

A method of producing electronic device packages is provided, consisting of the steps of shaping a package preform and heating the package preform in a nitrogen-containing atmoshpere to nitride the package preform. The shaped package preform may consist of package base, sidewall, conductor, resistor, or capacitor components. The package base and sidewall components may be formed of silicon powder. The method also accommodates the step of inserting a semiconducting material into the package preform and heating the semiconducting material component along with the package preform. The inserted semiconducting material component may be processed to define active electronic device areas on the component either before or after the step of heating the shaped package preform and inserted semiconducting material component. The package production methods of the invention provide the ability to produce reaction bonded structural and dielectric package components by way of a nitriding process that causes minimal overall shrinkage of the package. As a result, reaction formed electronic device packages of the invention may be shaped to finished dimensions before the nitriding process with complicated and tight-tolerance geometries of package structural, conducting, resistive, and capacitive components. The package production methods of the invention also provide the ability to interleave electronic device and packaging manufacturing sequence steps, resulting in increased manufacturing efficiency, as well as improved performance in the devices and packages produced. Device substrates or partially fabricated devices may be embedded into semi-finished packages, whereby completion of device fabrication coincides with completion of package fabrication. This makes possible the fabrication of active devices and circuits in a fully packaged environment.

A permeable base transistor (30) including a metal base layer (34) embedded in a semiconductor crystal (32) to separate collector (38) and emitter (40) regions and form a Schottky barrier with each is diclosed. The metal base layer has at least one opening (37) through which the crystal semiconductor (32) joins the collector (38) and emitter (40) regions. Ohmic contacts (42,44) are made to the emitter (38) and collector (40) regions. The width of all openings (37) in the base layer (34) is of the order of the zero bias depletion width corresponding to the carrier concentration in the opening. The thickness of the metal layer (34) is in the order of 10% of this zero bias depletion width. As a result, a potential barrier in each opening limits current flow over the lower portion of the bias range. With increasing forward base bias the potential in the openings, which is lower than along the metal of the base layer (34), is lowered sufficiently to permit substantial increase in the barrier limited current flow from the collector (38) to emitter (40).

Semiconductor embedded layer technology including permeable base

A permeable base transistor (30) including a metal base layer (34) embedded in a semiconductor crystal (32) to separate collector (38) and emitter (40) regions and form a Schottky barrier with each is disclosed. The metal base layer has at least one opening (37) through which the crystal semiconductor (32) joins the collector (38) and emitter (40) regions. Ohmic contacts (42,44) are made to the emitter (38) and collector (40) regions. The width of all openings (37) in the base layer (34) is of the order of the zero bias depletion width corresponding to the carrier concentration in the opening. The thickness of the metal layer (34) is in the order of 10% of this zero bias depletion width. As a result, a potential barrier in each opening limits current flow over the lower portion of the bias range. With increasing forward base bias the potential in the openings, which is lower than along the metal of the base layer (34), is lowered sufficiently to permit substantial increase in the barrier limited current flow from the collector (38) to emitter (40). A method of fabricating this transistor as well as methods for forming integrated circuit structures are also disclosed. Metal and other layers may be selectively embedded in semiconductor crystal. Embedded metal layers may serve as interconnections between devices. Devices may be in a stacked configuration.

Semiconductor embedded layer technology utilizing selective epitaxial

A layer of material such as the metal base of a transistor is embedded in single crystal. A layer of the material with small, uniformly dimensioned and uniformly spaced openings is formed on a single crystal substrate, and the single crystal is grown from the exposed portions of the substrate over the layer of material. For best results, the layer of material to be embedded is deposited relative to the crystal orientation to provide a much greater rate of crystal growth laterally across the layer than away from the crystal substrate. The method is particularly useful in fabricating a permeable base transistor having slits formed in the metal base layer. An integrated circuit can be fabricated by forming a pattern of conductive material on a single crystal, that pattern having continuous regions which inhibit further crystal growth and narrow regions or regions having openings therein which permit lateral crystal growth across those regions. In that way, the conductive pattern is selectively embedded with the continuous regions left exposed after crystal growth. Connections can be made between the exposed regions and a pattern on the new crystal layer. This method has particular usefulness in fabricating multi-level integrated circuits.

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Boxboro, MA, United States of America

R Allen Murphy