Freescale Semiconductor,inc.

Nxp Usa, Inc.

Quyen Pho

William C Moyer

Michael J Rochford

Jeffrey William Scott

Jehoda Refaeli

Jimmy Gumulja

Nancy Hing-Che Amedeo

Martin Mienkina

Avni Arora

A requestor of a data processing system provides read access requests, full write access requests with corresponding full write data each having a full-width data size, and partial write access requests with corresponding partial write data each having a partial-width data size onto a system interconnect. A memory array stores write data and corresponding error correction code (ECC) check bits in response to write access requests and provides read data and corresponding ECC check bits for the read data in response to read access requests. A memory controller executes a read-modify-write (RMW) sequence between a store buffer and the memory array to implement a partial write transaction in response to a partial write access request, in which the memory controller stores the partial write data into the store buffer upon receiving the partial write access request and suppresses signaling of ECC errors to the requestor during the RMW sequence.

Memory controller which implements partial writes with error signaling

Error detection circuitry is configured to receive raw read data from a memory, perform error detection in accordance with a single-bit error correction and double-bit error detection (SECDEC) error-correction code (ECC) on the raw read data, and provide a single bit correction indicator in response to performing the SECDEC ECC on the raw read data. Error correction circuitry is configured to provide corrected read data corresponding to the raw read data based at least on the single bit correction indicator. ECC checking circuitry is configured to generate a wrong operation indicator based at least on a parity of the raw read data, a parity of the corrected read data, and the single bit correction indicator, wherein the ECC checking circuitry is configured to assert the wrong operation indicator when at least one of the error detection circuitry or the error correction circuitry is not operating correctly.

Circuitry for checking operation of error correction code (ECC) circuitry

A data processing system includes an instruction pipeline, a bus interface unit, and a cache. The instruction pipeline is configured to assert a discard signal when a speculative read request is determined to have been mispredicted. The speculative read request has a corresponding access address. The bus interface unit is configured to communicate with an external system interconnect. The cache includes a cache array and cache control circuitry. The cache control circuitry is configured to receive the discard signal from the instruction pipeline and, when the discard signal is asserted after the access address has been provided to the external system interconnect by the bus interface unit in response to a determination by the cache control circuitry that the access address missed in the cache array, selectively store the read information returned from the access address into the cache array.

Data processing system with speculative fetching

A data processing system () includes a main list () of tasks, main scheduling scheme, a starvation list () of tasks, and a secondary scheduling scheme. A method identifies tasks in the main list that are potentially-starving tasks and places the potentially-starving tasks in the starvation list. A starvation monitor () controls starvation of tasks in the system by determining when to use the secondary scheduling scheme to schedule, for execution on a CPU (), a highest priority task in the starvation list prior to scheduling, pursuant to the main scheduling scheme, other tasks in the main list. The starvation monitor determines a number of times that a task in the main list is pre-empted, by other tasks in the main list, from being scheduled for execution on the CPU. A counter () is incremented each occasion that any task not in the starvation list is executed on the CPU.

Starvation control in a data processing system

A computer processing system includes a central processing unit (CPU) and logic instructions operable to, when a task ready to be scheduled for execution in the CPU () is the same as a task yielding to the task ready to be scheduled (-Y), retain context information for the yielding task in background registers in the CPU, and move the context information for the yielding task directly from the background registers to foreground registers in the CPU for the task ready to be scheduled (). The task ready to be scheduled is executed using the context information in the foreground registers ().

Systems and methods for improving data restore overhead in multi-tasking environments

When data in first and second requests from a processor does not reside in cache memory, a first data element responsive to the second request is received by a cache controller from an external memory module after a first data element responsive to the first request and before the second data element responsive to the first request. Ownership of a linefill buffer is assigned to the first request when the first data element responsive to the first request is received. Ownership of the linefill buffer is re-assigned to the second request when the first data element responsive to the second request is received after the first data element responsive to the first request is received.

Data processing system with cache linefill buffer and method of operation

A store gathering policy is enabled or disabled at a data processing device. A store gathering policy to be implemented by a store buffer can be selected from a plurality of store gathering polices. For example, the plurality of store gathering policies can be constrained or unconstrained. A store gathering policy can be enabled by a user programmable storage location. A specific store gathering policy can be specified by a user programmable storage location. A store gathering policy can be determined based upon an attribute of a store request, such as based upon a destination address.

Flexible control mechanism for store gathering in a write buffer

Methods and systems are disclosed for recovering dirty linefill buffer data upon linefill request failures. When a linefill request failure occurs and the linefill buffer has been marked as dirty, such as due to a system bus failure, the contents of the linefill buffer are pushed back to the system bus. The dirty data within the linefill buffer can then be used to update the external memory. The disclosed embodiments are useful for a wide variety of applications, including those requiring low data failure rates.

Methods and systems for pushing dirty linefill buffer contents to external bus upon linefill request failures

A snoop look-up operation is performed in a system having a cache and a first processor. The processor generates requests to the cache for data. A snoop queue is loaded with snoop requests. Fullness of the snoop queue is a measure of how many snoop requests are in the snoop queue. A snoop look-up operation is performed in the cache if the fullness of the snoop queue exceeds the threshold. The snoop look-up operation is based on a snoop request from the snoop queue corresponding to an entry in the snoop queue. If the fullness of the snoop queue does not exceed the threshold, waiting to perform a snoop look-up operation until an idle access request cycle from the processor to the cache occurs and performing the snoop look-up operation in the cache upon the idle access request cycle from the processor.

Snoop request arbitration in a data processing system

A method includes providing a cache; and providing a plurality of cache lines within the cache, wherein a first one of the plurality of cache lines has a tag entry and a data entry, wherein the tag entry has a parity field for storing one or more parity bits associated with a first portion of the tag entry, wherein the tag entry has an EDC field for storing one or more EDC check bits associated with a second portion of the tag entry and wherein the EDC check bits are used for detecting multiple bit errors, and wherein both the first parity field and the EDC field are stored in the tag entry of said first one of the plurality of cache lines.

Error detection schemes for a cache in a data processing system

A snoop look-up operation is performed in a system having a first cache and a first processor. The first processor generates access requests to the first cache for data. Snoop look-up operations are performed in the cache. The snoop look-up operations are based on snoop requests from a snoop queue. The snoop requests correspond to entries in the snoop queue. An access request from the first processor is performed in response to a consecutive number of snoop look-up operations exceeding a first limit. This is useful in avoiding having no processor operations while performing snoop look-up operations. Similarly, consecutive access requests can be counted and if a second limit is exceeded, a snoop look-up operation can be performed.

A processor and cache is coupled to a system memory via a system interconnect. A first buffer circuit coupled to the cache receives one or more data words and stores the one or more data words in each of one or more entries. The one or more data words of a first entry are written to the cache in response to error free receipt. A second buffer circuit coupled to the cache has one or more entries for storing store requests. Each entry has an associated control bit that determines whether an entry formed from a first store request is a valid entry to be written to the system memory from the second buffer circuit. Based upon error free receipt of the one or more data words, the associated control bit is set to a value that invalidates the entry in the second buffer circuit based upon the error determination.

Utilization of a store buffer for error recovery on a store allocation cache miss

Snoop requests are managed in a data processing system having a cache coupled to a processor that provides access addresses to the cache. Snoop queue circuitry provides snoop addresses to the cache via an arbiter. The snoop queue circuitry has a snoop request queue for storing a plurality of entries. Each entry of the snoop request queue that corresponds to a snoop request includes a snoop address and a corresponding status indicator. The corresponding status indicator indicates whether the snoop request has zero or more collapsed snoop requests having a common snoop address which have been merged to form the snoop request. The status indicator is used for debug and by fullness management logic to manage the capacity of the snoop request queue. A general collapsed status signal is generated to indicate whenever any snoop queue entry collapsing occurs.

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Pflugerville, TX, United States of America

Quyen Pho