Dell Products Inc.

Dell USA L P

Quy Hoang

Shawn Joel Dube

Timothy Michael Lambert

Wei G Liu

Mark W Shutt

Muhammed K Jaber

Andy Butcher

Theodore S Webb, Iii

Mukund Purshottam Khatri

Sandor Tibor Farkas

John Erven Jenne

Vadhiraj Sankaranarayanan

Pankaj Bishnoi

An information handling system includes a dual in-line memory module (DIMM) coupled to a memory controller via a memory channel. A processor during a first in time boot process of the information handling system determines a first environmental condition of the information handling system, and initializes the memory controller and the DIMM to determine a first set of initialization parameters for the memory controller and the DIMM. During a second in time boot process of the information handling system, the processor determines if a second environmental condition is different than the first environmental condition, if the second environmental condition is not different then to continue the second in time boot process without initializing the memory controller and the DIMM, and if the second environmental condition is different then to initialize the memory controller and the DIMM to determine a second set of initialization parameters for the memory controller and the DIMM.

Dual inline memory module with multiple boot processes based on first and second environmental conditions

An information handling system includes a dual in-line memory module (DIMM) coupled to a memory controller. The memory controller provides interrupts to a processor each time a read transaction from the DIMM results in a correctable read error. The processor instantiates a failure predictor that receives the interrupts, accumulates a count of the interrupts, and provides an error indication when the count exceeds an error threshold. In accumulating the count, the failure predictor increments the count each time the predictor receives a particular interrupt and decrements the count in accordance with an error leak rate. The error leak rate has a first value when a training coefficient for the DIMM is greater than a deviation threshold, and has a second value when the training coefficient for the DIMM is less than the deviation threshold.

System and method for improved handling of memory failures

Systems and methods for reducing problems and disadvantages associated with traditional approaches to providing accessibility and redundancy for access controller storage media are provided. A method for providing accessibility for storage media of an access controller in an information handling system may include: (i) emulating the storage media such that the storage media appears to an operating system executing on the information handling system as storage media locally attached to the information handling system; (ii) mounting the storage media such that data may be communicated between the storage media and a processor integral to the access controller; (iii) mounting a portion of a network-attached storage remote to the information handling system such that data may be communicated between the portion of the network-attached storage and the processor; and (iv) maintaining redundancy between the storage media and the portion of network-attached storage in accordance with a redundancy policy.

System and method for providing accessibility for access controller storage media

A DIMM includes a DRAM device and a non-volatile memory device. The DIMM is configured to determine that first data stored on the DRAM device is modified data and that second data stored on the DRAM device is unmodified data, and perform a save data operation to transfer the data from the DRAM device to the non-volatile memory device, wherein the save data operation comprises transferring the first data and not transferring the second data.

System and method for storing modified data to an NVDIMM during a save operation

A method comprises signing boot code with a public/private cryptographic key pair, and writing to storage the boot code, the public cryptographic key, and the signed boot code.

Arbitrary code execution and restricted protected storage access to trusted code

Systems and methods for accessing configurable storage resources are provided. In some embodiments, an access controller for use in an information handling system is provided. The access controller may include a processor, a plurality of configurable storage resources coupled to the processor, and a network interface communicatively coupled to the processor and configured to allow simultaneous in-band and out-of-band access to the plurality of configurable storage resources. The processor may be configured to determine a configuration of the plurality of configurable storage resources, map the configuration to the plurality of configurable storage resources, and execute an application for managing the simultaneous access of the plurality of configurable storage resources.

System and method for accessing storage resources

Methods and systems for binding a removable trusted platform module (TPM) subsystem module to an information handling system to provide a core root of trust for the information handling system without requiring soldering down or other hard and permanent (non-removable) attachment of a TPM device to the information handling system planar (e.g., motherboard). The removable TPM subsystem module may be a plug-in module that may be removed from the information handling system planar (e.g., motherboard), while at the same time maintaining the transitive chain of trust, and being capable of remotely attesting its trusted state. An information handling system platform may be provided that has the capability and flexibility of supporting multiple TPMs on the same system planar.

Methods and systems for binding a removable trusted platform module to an information handling system

The present disclosure further relates to information handling systems with failover support for booting an embedded hypervisor, the information handling system. For example, an information handling system with failover support may comprise a processor; one or more applications configured to be executed, at least in part, by the processor; a memory communicatively coupled to the processor and comprising a basic input/output system (BIOS), the BIOS comprising a BIOS universal serial bus (USB) driver, the BIOS USB driver comprising a mass storage device driver; a primary internal embedded hypervisor non-volatile memory (NVM) card communicatively coupled to the memory, the first NVM card comprising a first bootable hypervisor image; and a back up internal embedded hypervisor NVM card communicatively coupled to the memory, the second NVM card comprising a second bootable hypervisor image.

Systems and methods to provide failover support for booting embedded hypervisor from an internal non-volatile memory card

A system and method for providing a power supply dual remote sense. A power supply with a positive remote sense input is coupled to first and second load positions. The load positions are each coupled to a pull-down circuit to provide first and second voltages, respectively, to the inputs of the pull-down circuit. The pull-down circuit output is coupled to the positive remote sense input of the power supply. The voltage level of the pull-down circuit output is no greater than either of the first or second voltages provided at its inputs.

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Round Rock, TX, United States of America

Quy Hoang