Shanghai Zhaoxin Semiconductor Co., Ltd.

Qunchao Feng

Jiangbo Wang

Jinglong Liu

Jintao Wang

Yongfeng Song

Yankui Niu

Yanliang Liu

Xiaoliang Ji

Wenting Wu

Xiuli Guo

A processor includes at least one socket and at least one memory. Each socket includes a first die and a second die. The first die receives a boot-enable signal and an internal boot-enable signal to execute a boot procedure, and outputs a boot-completion signal after completing the boot procedure. The second die receives the internal boot-enable signal and the boot-completion signal from the first die to execute the boot procedure. The second die is electrically connected to the first die through a communication bus. The memory is electrically connected to the second die. When the first die executes the boot procedure, the first die accesses the memory through the communication bus and the second die.

Processor and booting method thereof

A booting technology for a multi-die and multi-core computing platform is shown. A storage device stores numberfirmware code and numberfirmware code. A master die is coupled to the storage device through a bus and accesses the numberfirmware code from the storage device through the bus. A first slave die is also coupled to the storage device through the bus. However, instead of accessing the storage device for the numberfirmware code, the first slave die monitors the bus and retrieves the numberfirmware code, accessed by the master die, from the bus. The master die further accesses the numberfirmware code from the storage device through the bus. The master die executes the numberfirmware code to operate the master die and the first slave die to boot the system and start up the platform.

Multi-die and multi-core computing platform and booting method for the same

A multi-die and multi-core computing platform in which multiple dies share the same storage device for firmware code storage is shown. After a slave die loads #1 firmware code from the storage device through a bus, the right to use the bus is released by the slave die and the slave die outputs a #0 enable signal to a master die. According to the #0 enable signal, the master die gains the right to use the bus. Through the bus, the master die loads #0 firmware code from the storage device. The slave die executes the #1 firmware code and the master die executes the #0 firmware code to initialize a link between the master and slave dies.

Multi-die and multi-core computing platform and booting method therefor

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Beijing, China

Qunchao Feng