Stmicroelectronics (rousset) Sas

Stmicroelectronics (crolles 2) Sas

Quentin Hubert

Abderrezak Marzaki

Stephan Niel

Arnaud Regnier

Thomas Cabout

Julien Delalleau

Pascal Fornara

Christian Rivero

Matthias Vidal-Dho

In one embodiment, a non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.

Non-volatile memory device with vertical state transistor and vertical selection transistor

Moisture that is possibly present in an integrated circuit is detected autonomously by the integrated circuit itself. An interconnect region of the integrated circuit includes a metal level with a first track and a second track which are separated by a dielectric material. A detection circuit applies a potential difference between the first and second tracks. A current circulating in one of the first and second tracks in response to the potential difference is measured and compared to a threshold. If the current exceeds the threshold, this is indicative of the presence of moisture which renders said dielectric material less insulating.

Method for detecting moisture in an integrated circuit, and associated integrated circuit

A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

Integrated circuit with vertically structured capacitive element, and its fabricating process

A non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.

An integrated electronic circuit includes a semiconductor substrate with a semiconductor well that is isolated by a buried semiconductor region located under the semiconductor well. A vertical MOS transistor formed in the semiconductor well includes a source-drain region provided by the buried semiconductor region. Backside thinning of the semiconductor substrate is detected by biasing the vertical MOS transistor into an on condition to supply a current and then comparing that current to a threshold. Current less than a threshold is indicative that the semiconductor substrate has been thinned from the backside.

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Marseilles, France

Quentin Hubert