Tektronix, Inc.

Que Thuy Tran

David L Kelly

Patrick A Smith

Shane A Hazzard

Daniel G Knierim

Douglas A Blegen

John J Pickerd

John C Calvin

Kayla R Klingman

John C De Lacy

Dennis Keldsen

Michael M Heidling

John C Delacy

A test and measurement apparatus, system, and method for synchronizing an acquisition or triggering system to a specific burst of interest. The subject apparatus and method triggers on varying energy content of a signal qualified by time in the presence of high-frequency input signal bursts, by using an adjustable pulse width envelope detector, disposed in the signal path of the trigger circuitry, as a digital rectifier or to otherwise process and extract an envelope signal. An RF envelope probe having an analog envelope detector among other suitable components is disclosed. A method is implemented for isolating an interval of interest in a signal under test. An envelope detector circuit produces an envelope signal from the signal. Trigger circuitry receives the envelope signal from the envelope detector, and isolates the interval of interesting in the signal under test using the envelope signal.

Apparatus and method for performing burst triggering in a test and measurement instrument

Embodiments of the invention include methods, apparatuses, and systems for automatically identifying a synchronization sub-pattern associated with a test pattern. A test and measurement instrument is triggered in response to a first instance of a trigger pattern in a data stream. A trigger-to-trigger counter begins counting at the time of the first trigger event. The test and measurement instrument is again triggered in response to a second instance of the trigger pattern in the data stream. The count is ended at this time. The count is then compared to a predefined length of the test pattern, and if equal, it is automatically determined that the trigger pattern is the unique synchronization sub-pattern associated with the test pattern.

Test and measurement instrument with auto-sync for bit-error detection

A test and measurement instrument includes a pattern detector for detecting a beginning sequence in a signal under test (SUT), and generates a synchronization signal. In response to the synchronization signal, a memory outputs a reference test pattern. A symbol comparator compares the reference test pattern with the SUT. The symbol comparator can produce a symbol error rate. One or more 8b to 10b converters receives the SUT from the input and the digitized data from the memory, and converts the data from an 8b coded format to a 10b coded format. A bit comparator compares the 10b coded reference test pattern with the 10b coded SUT in response to the symbol comparator. The bit comparator is coupled to a bit error counter, which produces a bit error rate independent of any disparity errors that may be present in the incoming digitized data received by the test and measurement instrument.

Method and apparatus for measuring symbol and bit error rates independent of disparity errors

A test and measurement instrument including an input configured to receive a signal and output digitized data; a memory configured to store reference digitized data including a reference sequence; a pattern detector configured to detect the reference sequence in the digitized data and generate a synchronization signal in response; a memory controller configured to cause the memory to output the reference digitized data in response to the synchronization signal; and a comparator configured to compare the reference digitized data output from the memory to the digitized data.

Test and measurement instrument with bit-error detection

A blanking primitive masking circuit has a detection and handling circuit that receives data containing blanking primitives. The detection and handling circuit generates a dynamic blanking signal when blanking primitives are detected. The received data is delayed and provided to a pattern detector that generates a synchronization signal provided to a memory and a phase sync signal provided to the detection and handling circuit and to a comparator. The comparator receives reference data from the memory, the delayed data, and the dynamic blanking signal. The comparator compares the reference data with the delayed data and generates bit error outputs from mismatched reference data bits and delayed data bits when the dynamic blanking signal from the detection and handling circuit is absent and suppressing the generation bit error outputs when the blanking primitive are in the delay data and the dynamic blanking signal is present.

Blanking primitives masking circuit

A method for improving performance and flexibility of serial data analysis in test instruments, is independent of data bit rate, encoding scheme or communication protocol embodied in the serial data. The serial data is input to a transmitter section, where it is demultiplexed into a plurality of multi-bit lanes, such as n bits for each of N lanes. The N lanes are then encoded into characters, the encoded N lanes having m bits per lane where m&#x3e;n. Bit stuffing is used to adjust the data rate and/or to insert qualifiers. The stuffed, encoded N lanes are then multiplexed into N serial lanes, which are output from the transmitter section for input to a receiver section at a data rate that is optimal for the receiver section. In the receiver section the N lanes are deserialized, decoded and input to a word recognizer to generate a trigger event signal.

Serial data analysis improvement

A pattern sequence and state transition trigger generator provides a trigger when a specified transition from one pattern/state to another pattern/state occurs in a set of input signals. Decoders detect each specified pattern/state from the set of input signals to produce a prior value and a current value representing the transition. The prior value is slightly delayed and combined with the current value to produce an overlap when the specified transition occurs, which in turn generates the trigger.

Pattern sequence and state transition triggers

A system, method and apparatus for triggering a plurality of test and measurement instruments in a substantially simultaneous manner logically combines a trigger enable signal provided by each of a plurality of signal processing devices to produce a combined trigger signal. The combined trigger signal then triggers each of the plurality of signal Processing devices.

Method and apparatus providing multiple channel multiple instrument triggering

System and apparatus enabling the use of a single cable to communicate triggering information between each of a plurality of signal acquisition devices and, illustratively, an external trigger control unit. A combined trigger signal is produced only when each trigger condition of each signal acquisition device is true. Thus, all of the signal acquisition devices will be triggered substantially simultaneously.

Method and apparatus providing single cable bi-directional triggering between instruments

An advanced trigger circuit includes two trigger decoders, each triggering on one of respective pluralities of continuous-time trigger events. In one embodiment, a programmable timer begins timing in response to an output signal of the first trigger decoder and generates an end-of-time signal at the expiration of its time period. A reset circuit resets the first trigger decoder if the second selected continuous-time trigger event failed to occur before the end-of-time signal was generated. In another embodiment, a reset decoder generates a reset signal in response to an occurrence of a selected continuous-time trigger event. The reset circuit is responsive to the reset signal for resetting the first trigger decoder if the second selected continuous-time trigger event failed to occur before the reset signal was generated. In other embodiments, the advanced trigger circuit triggers on a serial lane skew violation or on a beacon width violation.

Oscilloscope having advanced triggering capability

A system includes a plurality of digital storage oscilloscopes (DSOs) in which each DSO requires a respective temporal portion of a signal under test (SUT) according to a synchronized triggering signal and respective post-trigger count periods such that a plurality of acquisition records may be concatenated to produce a longer acquisition record.

Method and apparatus providing concatenated data from multiple signal acquisition devices

A combined analog and DSP trigger system for a digital storage oscilloscope (DSO) enables the DSO to real-time trigger on events in an input analog signal based on traditional trigger events in the input analog signal and/or predetermined anomalous events detected in digitized samples of the input analog signal. A processor receives the digitized samples at the input of an acquisition memory to detect the anomalous events and provides an event detect signal to the trigger system. Predetermined amounts of the digitized samples around the events are acquired in an acquisition memory for further processing and display.

Combined analog and DSP trigger system for a digital storage oscilloscope

A system comprising a plurality of digital storage oscilloscopes (DSOs) in which each DSO acquires a common signal under test (SUT) according to respective clock signals having common frequency parameters and respective phase parameters such that a plurality of acquisition records may be interleaved to produce a higher effective resolution acquisition record.

Growing community of inventors

Beaverton, OR, United States of America

Que Thuy Tran