Intel Corporation

Quang T Le

Rajesh Poornachandran

Ravishankar Iyer

Blaise B Fanning

Ioannis T Schoinas

Daniel Cutter

Sunil Kumar

Ashish V Choubal

Harlan Titus Beverly

Bradley John Booth

Jose Niell

Ajaya V Durg

Vasudev Bibikar

Ravi Kolagotla

Ramadass Nagarajan

Christopher T Foulds

Anil K Sabbavarapu

James A Bish

Jain Philip

Arpit Shah

Madhu Gumma

Moorthy Rajesh

Murali Chilukoor

Ranjani Sridharan

Zhe Zhao

Nabil F Kerkiz

Ryan R Pinto

In some examples, a system can include a microcontroller to initialize a counter to a predetermined value for each image component of an image data slice. The microcontroller can also store a number of received bits for each image component in a data structure and generate a pre-allocation signal indicating that additional bits of data for one of the image components are to be requested and stored in the data structure, wherein the pre-allocation signal is to be generated in response to determining that the counter is below the predetermined value. The microcontroller can also increase the counter by the predetermined value and transmit an address from the data structure to a display device in response to detecting a valid signal.

Transmitting display data

Technologies for low-power display refresh standby include a computing device with a display such as an LCD panel. The computing device may include a system-on-a-chip (SoC) with a processor, I/O subsystem, display controller, and memory. When the computing device determines that a display image is static, the computing device enters a low-power display refresh standby mode, powering down unneeded components of the SoC such as processor cores, peripheral devices, and memory other than a dedicated display buffer. The display controller may access the dedicated display buffer via the I/O subsystem and output the image to the display. The computing device may power down the I/O subsystem and the dedicated display buffer when a display controller FIFO is full of image data, and periodically power on the I/O subsystem and display buffer to fill the display controller FIFO. Other embodiments are described and claimed.

Technologies for low-power standby display refresh

In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated order identifier and a deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.

Method, apparatus, system for representing, specifying and using deadlines

Methods and apparatus to perform security related operations on received signals are described. In one embodiment, a security device may perform security related operations on received signals and a logic (such as an Ethernet controller) may include an interface to provide communication with the security device. Other embodiments are also disclosed.

Methods and apparatus to perform security related operations on received signals

A method that includes determining a pending data packet count for one or more data packets associated with data to be forwarded from a node to another node on a communication link and then comparing the pending data packet count to a threshold data packet count value. The method further includes forwarding the one or more data packets to the other node at a rate based on the comparison.

Data packet rate control

Described are a device and system to transmit data to or receive data from one or more data lane interfaces. Each data lane interface may be capable of transmitting a serial data signal to or receiving a serial data signal from a data lane in a device-to-device interconnection. An effective data rate may be varied based, at least in part, upon a number of the data lane interfaces actively transmitting a serial data signal to or receiving a serial data signal from the device-to-device interconnection.

Scalable device-to-device interconnection

Provided are a method, system, and program for managing Input/Output (I/O) requests in a cache memory system. A request is received to data at a memory address in a first memory device, wherein data in the first memory device is cached in a second memory device. A determination is made as to whether to fetch the requested data from the first memory device to cache in the second memory device in response to determining that the requested data is not in the second memory device. The requested data in the first memory device is accessed and the second memory device is bypassed to execute the request in response to determining not to fetch the requested data from the first memory device to cache in the second memory device.

Managing input/output (I/O) requests in a cache memory system

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Austin, TX, United States of America

Quang T Le