Amdahl Corporation

Quang H Nguyen

Stephen J Rawlinson

Allan J Zmyslowski

Robert G Stebbins

Eugene T Wang

Arun Shah

Jeffrey L Baker

Carolee V Newcomb

Stephen M Simmonds

Duncan Penman

Glenn D Grant

R Morse Wade

Armand Minnie

Jon K Lexau

Allan Zymslowski

Robert A Shaw

A bypass means is provided for bypassing a system clock disabling signal around a conventional system clock disabling signal processing path to reduce the amount of delay between the occurrence of the disabling signal and a stopping of the system clock.

Apparatus and method for immediately stopping clocks

An approach to error assessment in computer systems is based on storing important state information while the machine is operating in a trace memory for each cycle of the clock. The trace memory is then coupled through the scan interface or otherwise to the service processor for use in analyzing the error. A set of signal lines in the data processing system is connected in parallel to the input port of the trace memory. Storing logic is coupled to the processor clock and to the input port of the memory, for storing information from the set of signal lines in successive locations in the trace memory in response to successive cycles of the clock. The output port of the trace memory is coupled to the service processor. The system also includes logic which counts the number of cycles of the clock after detection of an error until stopping of the clock and a system for tagging storage locations in the trace memory that correspond to cycles in which an error was detected.

Method and apparatus for tracing multiple errors in a computer system

An error detection scan tree apparatus and method including a plurality of error detection devices in which an error signal generated by an error detection device is propagated from the detection device through the scan tree of minimalistic structure to an error servicing unit. A plurality of scan out points are provided at specific locations within the scan tree that are capable of non-disruptively latching an error signal propagating therethrough so as to facilitate a more efficient scan out of the state of the system upon the occurrence of an error.

Error determination scan tree apparatus and method

A timer unit that permits individual timer registers to be taken offline from the timer complex. A single register is taken offline instead of checkstopping the entire computer system due to a damaged timer, for example, thereby reducing system outages and thus providing increased availability of the system.

Method for reconfiguring individual timer registers offline

A computer system having a number of circuits and error detection circuitry for detecting errors in the circuits and providing error signals. Error recovery is provided by detecting an error with checking logic, turning off system clocks and invoking error recovery software, executing recovery software to recover from the error and set an action latch, turning on system clocks, taking hardware recovery action in response to the action latch, resetting the action latch and continue processing. Action latches are used extensively throughout the computer system.

Invoking hardware recovery actions via action latches

The invention provides a method and apparatus for localizing error recovery activities to specific ones of logically parallel processes ongoing within a computer and to the initiators of error-infected ones of such processes.

Method and apparatus for providing retry coverage in multi-process

A divider, which performs division in a base other than 2, that reduces in most cases the number of cycles it takes to generate each quotient digit. This involves predicting the minimum possible quotient digit in response to leading digits of the partial remainder and of the divisor. The predicted minimum possible quotient digit times the divisor is then subtracted from the partial remainder. If the result of the subtraction is less than the divisor, the predicted least possible quotient digit is the correct quotient digit. If the result of the subtraction is greater than the divisor, the divisor is subtracted iteratively from that result until the partial remainder falls below the value of the divisor. For each subtraction, the predicted quotient digit is incremented by one, so that a correct quotient digit results at the end of the iteration.

Divider with quotient digit prediction

A microword controlled computer system with an apparatus for performing a pseudo branch. The pseudo branch involves the re-execution of a selected microword in a microword register. The computer system comprises a microword register, N control stores, an apparatus for selectively transferring a microword from one of the N control stores to the microword register, an apparatus coupled to said microword register for executing each microword in said microword register and an apparatus for branching to N+1 targets wherein each one of N of said N+1 targets comprises a microword from one of said N control stores and one of said N+1 targets is a current microword in said microword register.

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San Jose, CA, United States of America

Quang H Nguyen