International Business Machines Corporation

Quan Nguyen

Hung Qui Le

Paul Joseph Jordan

John Stephen Muhich

Hoichi Cheong

Ivan Vo

An output signal is output to a selected one of first and second output nodes in response to an event in which a control node transitions from a first logic state to a second logic state. The selected one of the first and second output nodes is selected in response to a logic state of an input node during the event. A minimum setup time for the logic state of the input node to be stable before the control node transitions to the second logic state is shorter than a minimum time for inverting the logic state of the input node.

Circuitry and method for latching information

According to one aspect of the invention, a method is provided for maintaining the state of a processor having a plurality of physical registers and a rename register map which stores rename pairs that associate architected and physical registers, the rename register map having a plurality of entries which are associated with the physical registers, individual entries having an architected register field, an architected status bit and a history status bit. In one version, the method includes the steps of dispatching an instruction which targets an architected register; determining a presently architected entry in the rename register map in which an architected pointer in the architected register field of the entry matches the architected register pointer of the architected register targeted by the dispatched instruction and the architected status bit is set; resetting the architected status bit; setting the history status bit in the entry and saving the physical register pointer to a checkpoint recovery table if the dispatched instruction is interruptible or if the architected register of the dispatched instruction has not been targeted since the latest dispatched interruptible instruction; determining a next available rename register map entry; writing a pointer to the architected register targeted by the instruction into the architected register field and setting the architected status bit in the next available rename register map entry.

Method and apparatus for reducing the number of rename registers in a

First current is conducted through a first path to adjust a voltage at a node toward a predetermined level in response to the voltage being within a first subrange of voltages. Second current is conducted through a second path to adjust the voltage at the node toward the predetermined level in response to the voltage being within a second subrange of voltages.

Growing community of inventors

Austin, TX, United States of America

Quan Nguyen