Qualcomm Incorporated

Quaeed Motiwala

Luca Blessent

Li Feng Zhang

Inyup Kang

Haitao Zhang

Gilbert Christopher Sih

Qiuzhen Zou

Way-Shing Lee

Deepu John

Avneesh Agrawal

Paul E Bender

Brian K Butler

Christopher Cooper Riddle

Sanjay K Jha

Jian Lin

Robert Fuchs

Charles E Sakamaki

Prashant A Kantak

Shih-Yi Yeh

Quizhen Zou

The frame of data is partitioned into a plurality of portions of data symbols. A plurality of channel elements is assigned to demodulate data symbols of correspondingly the plurality of portions of data symbols. The number of the plurality of portions of data symbols is higher in a case at high data rate than a case at low data rate.

Method and apparatus for efficient use of communication resources in a communication system

The punctured pilot channel comprises information symbols of uncertain sign punctured into a sequence of pilot channel symbols of predetermined sign. The apparatus includes an information sign demodulation circuit for determining the sign of the information symbols in response to the pilot channel symbols. A continuous pilot generator generates a non-punctured pilot channel of predetermined sign from the information symbols and the pilot channel symbols. In a first embodiment, the information sign demodulator further comprises a dot product circuit for calculating a dot product of the pilot channel symbols and the punctured information symbols, and a threshold comparator for comparing the dot product to a predetermined threshold.

Method and apparatus for processing a punctured pilot channel

A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories. An instruction decoder decodes the instructions from the instruction memory and generates control signals that cause data to be exchanged between the various registers, data memories, and functional units, allowing multiple operations to be performed during each clock cycle.

Multiple-data bus architecture for a digital signal processor using variable-length instruction set with single instruction simultaneous control

Techniques for coherent demodulation in the presence of phase discontinuities is described. In the exemplary embodiment, times when phase discontinuities occur are known apriori by a receiver in which demodulation is being performed. In an alternate embodiment, the discontinuity location is signaled to the receiver in advance by the transmitter which generates the signals being demodulated. A pilot signal is prepared for optimal coherent demodulation by the use of two filters: one capable of withstanding the effects of phase discontinuity; a second providing superior filtering performance than the first so long as phase discontinuities are not present. Both filters are simultaneously operated. However, the superior performing filter is selected for use in demodulation whenever possible.

Coherent demodulator for use in the presence of phase discontinuities

The present invention is a novel and improved method and circuit for digital signal processing. One aspect of the invention calls for the use of a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. Furthermore, additional aspects of the invention are realized by having instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. Thus, multiple operations are performed during each clock cycle, reducing the total number of clock cycles necessary to perform a task. The exemplary DSP includes a set of three data buses over which data may be exchanged with a register bank and three data memories. The use of more than two data buses, and especially three data buses, realizes another aspect of the invention, which is significantly reduced bus contention. One embodiment of the invention calls for the data buses to include one wide bus and two narrow buses. The wide bus is coupled to a wide data memory and the two narrow buses are coupled to two narrow data memories. Another aspect of the invention is realized by the use of a register bank that has registers accessible by at least two processing units. This allows multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. The processing units in the exemplary embodiment of the invention include an arithmetic logic (ALU) and a multiply-accumulate (MAC) unit. When combined with the use of the multiple bus architecture, highly parallel instructions, or both, an additional aspect of the invention is realized where highly pipelined, multi-operation, processing is performed.

Variable length instruction decoder

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San Diego, CA, United States of America

Quaeed Motiwala