International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Globalfoundries Singapore Pte. Ltd.

Conexant Systems, Inc.

Newport Fab, LLC

Globalfoundries U.S. 2 LLC

Qizhi Liu

Vibhor Jain

David Louis Harame

John Joseph Pekarik

Alvin Jose Joseph

Renata A Camillo-Castillo

Anthony K Stamper

James Stuart Dunn

James William Adkisson

Peter B Gray

Zhong-Xiang He

Kevin K Chan

Marwan H Khater

Steven M Shank

Judson Robert Holt

John J Ellis-Monaghan

Robert K Leidy

Peng Cheng

James Randall Elliott

Mark David Jaffe

Andreas Daniel Stricker

Natalie Barbara Feilchenfeld

Peter John Geiss

Ramana Murty Malladi

Erik Mattias Dahlstrom

Jeffrey P Gambino

BethAnn Rainey

Yusheng Bian

Jeffrey Bowman Johnson

Herbert Lei Ho

Thomas N Adam

Rajendran Krishnasamy

Bradley Alan Orner

Russell T Herrin

Zhenzhen Ye

Joseph R Greco

Aaron Vallett

Christa Regina Willets

John J Benoit

Edward J Nowak

Shyue Seng Tan

Ping-Chuan Wang

Hanyi Ding

Randy William Mann

William F Clark, Jr

Yun Shi

Kathryn Turner Schonenberg

Mark Levy

Yung Fu Chong

Xinshu Cai

Claude Ortolland

Robert J Purtell

Kimball M Watson

Gary L Milo

Beth Ann Rainey

Jae-Sung Rieh

Kangguo Cheng

Alexander Reznicek

Ali Khakifirooz

Jed Hickory Rankin

Yanli Zhang

Robert Mark Rassel

Edmund Juris Sprogis

James Albert Slinkman

Bin Zhao

James Spiros Nakos

Robert Allen Groves

You Qian

Stephen Arthur St Onge

Francois Pagette

Mete Erturk

Cameron E Luce

Mattias E Dahlstrom

Maureen R Brongo

Vikas Kumar Kaushal

Dinh Dang

Joan Josep Giner De Haro

Mark D Levy

Devendra K Sadana

Kirk David Peterson

Siva P Adusumilli

Xuefeng Liu

Xusheng Kevin Wu

Viorel C Ontalus

William Joseph Murphy

Paul Francis Fortier

Zhijian Yang

Richard John Rassel

David Charles Sheridan

Nicholas A Polomoff

Yves T Ngu

Ramsey M Hazbun

Uzma B Rana

Humberto Campanella-Pineda

Marc Waine Cantell

Keith Donegan

Ian McCallum-Cook

Humberto Campanella Pineda

Elizabeth Strehlow

Brennan J Brown

The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a stepped emitter and methods of manufacture. The structure includes: a collector; a base over the collector; and an emitter over the base, the emitter comprising at least one stepped feature over the base.

Bipolar transistor with stepped emitter

The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted 'T' shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.

Transistor with wrap-around extrinsic base

Disclosed are a structure including a transistor and a method of forming the structure. The transistor includes an emitter region with first and second emitter portions. The first emitter portion extends through a dielectric layer. The second emitter portion is on the first emitter portion and the top of the dielectric layer. An additional dielectric layer covers the top of the second emitter portion. The second emitter portion and the dielectric and additional dielectric layers are wider than the first emitter portion. At least a section of the second emitter portion is narrower than the dielectric and additional dielectric layers, thereby creating cavities positioned vertically between edge portions of the dielectric and additional dielectric layers and positioned laterally adjacent to the second emitter portion. The cavities are filled with dielectric material or dielectric material blocks the side openings to the cavities creating pockets of air, of gas or under vacuum.

Vertical bipolar junction transistor and method

The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises mono-crystal silicon based material; an intrinsic base under the emitter region and comprising semiconductor material; and an extrinsic base surrounding the emitter and over the intrinsic base.

Structures including an edge coupler, and methods of fabricating a structure that includes an edge coupler. The structure includes an edge coupler having a waveguide core with an end surface and a longitudinal axis. The end surface defines a plane tilted in a first direction at a first acute angle relative to the longitudinal axis and tilted in a second direction at a second acute angle relative to the longitudinal axis. The second direction differs from the first direction.

Spot-size converters with angled facets

Embodiments of the disclosure provide an optical antenna for a photonic integrated circuit (PIC). The optical antenna includes a semiconductor waveguide on a semiconductor layer. The semiconductor waveguide includes a first vertical sidewall over the semiconductor layer over the semiconductor layer. A plurality of grating protrusions extends horizontally from the first vertical sidewall of the semiconductor waveguide.

Optical antenna for photonic integrated circuit and methods to form same

Embodiments of the disclosure provide an optical antenna for a photonic integrated circuit (PIC). The optical antenna includes a vertically oriented semiconductor waveguide with a first end on a semiconductor layer. The vertically oriented semiconductor waveguide includes a first sidewall and a second sidewall opposite the first sidewall. A reflective material is along the second sidewall of the vertically oriented semiconductor waveguide. A first plurality of grating protrusions extends from the first sidewall of the vertically oriented semiconductor waveguide.

Optical antenna with reflective material for photonic integrated circuit and methods to form same

Structures for a grating coupler and methods of fabricating a structure for a grating coupler. The structure includes a grating coupler having a central portion and edge portions. The central portion and the edge portions define a sidewall, and the central portion and the edge portions have a first longitudinal axis along which the edge portions are arranged in a spaced relationship. Each edge portion projects from the sidewall at an angle relative to the first longitudinal axis. A waveguide core is optically coupled to the grating coupler. The first longitudinal axis is aligned in a first direction, and the waveguide core has a second longitudinal axis that is aligned in a second direction different from the first direction.

Angled grating couplers with inclined side edge portions

Aspects of the disclosure provide an integrated circuit (IC) structure with a bipolar transistor stack within a substrate. The bipolar transistor stack may include: a collector, a base on the collector, and an emitter on a first portion of the base. A horizontal width of the emitter is less than a horizontal width of the base, and an upper surface of the emitter is substantially coplanar with an upper surface of the substrate. An extrinsic base structure is on a second portion of the base of the bipolar transistor stack, and horizontally adjacent the emitter. The extrinsic base structure includes an upper surface above the upper surface of the substrate.

Integrated circuit structure and method for bipolar transistor stack within substrate

The present disclosure relates to semiconductor structures and, more particularly, to virtual bulk in semiconductor on insulator technology and methods of manufacture. The structure includes a heterojunction bipolar transistor formed on a semiconductor on insulator (SOI) wafer with a doped sub-collector material in a buried insulator region under a semiconductor substrate of the SOI wafer.

Virtual bulk in semiconductor on insulator technology

Device structures and fabrication methods for heterojunction bipolar transistors. Trench isolation regions are positioned in a semiconductor substrate to define active regions. A base layer includes first sections that are respectively positioned over the active regions and second sections that are respectively positioned over the trench isolation regions. Emitter fingers are respectively positioned on the first sections of the base layer. The first sections of the base layer include single-crystal semiconductor material, and the second sections of the base layer include polycrystalline semiconductor material. The second sections of the base layer are spaced in a vertical direction from the trench isolation regions to define a first cavity that extends about a perimeter of the base layer and second cavities that are connected to the first cavity.

Heterojunction bipolar transistors with undercut extrinsic base regions

The present disclosure relates to semiconductor structures and, more particularly, to a device with a marker layer and methods of manufacture. The device includes: a collector region; an intrinsic base region above the collector region; an emitter region comprising emitter material and a marker layer vertically between the intrinsic base region and the emitter material; and an extrinsic base region in electrical contact with the intrinsic base region.

Heterojunction bipolar transistor with marker layer

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region in a substrate; a collector region above the sub-collector region, the collector region composed of semiconductor material; an intrinsic base region composed of intrinsic base material surrounded by the semiconductor material above the collector region; and an emitter region above the intrinsic base region.

Heterojunction bipolar transistors

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes a collector region composed of semiconductor material; at least one marker layer over the collector region; a layer of doped semiconductor material which forms an extrinsic base and which is located above the at least one marker layer; a cavity formed in the layer of doped semiconductor material and extending at least to the at least one marker layer; an epitaxial intrinsic base layer of doped material located within the cavity; and an emitter material over the epitaxial intrinsic base layer and within an opening formed by sidewall spacer structures.

Heterojunction bipolar transistor

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Lexington, MA, United States of America

Qizhi Liu