United Microelectronics Corp.

Globalfoundries Singapore Pte. Ltd.

Apple Inc.

Qiuji Zhao

Chi Ren

Liang Yi

Zhiguo Li

Boon Keat Toh

Bai Yen Nguyen

Yoke Weng Tam

Chandrasekar Venkataramani

Koe Sun Pak

Wei Zhang

Liang Zhao

Sung Chang Lee

Xiaoguang Yang

Xiaofeng Yu

Yue Shen

Wendong Zhong

Bowen Cheng

Yue Hang

Weiqi Pan

The present disclosure generally relates to methods and user interfaces for authentication, including providing authentication at a computer system in accordance with some embodiments.

User interfaces for authenticating to perform secure operations

A structure of memory device includes an active region in a substrate, a dielectric layer on the active region, and a floating gate disposed on the dielectric layer. The active region extends along a first direction in a top-view. The floating gate includes a first protruding structure extending along the first direction from a sidewall of the floating gate protruding from a top surface of the substrate. The whole of the first protruding structure is located in the active region.

Structure of memory device having floating gate with protruding structure

A structure of memory device includes trench isolation lines in a substrate, extending along a first direction. An active region in the substrate is between adjacent two of the trench isolation lines. A dielectric layer is disposed on the active region of the substrate. A floating gate corresponding to a memory cell is disposed on the dielectric layer between adjacent two of the trench isolation lines. The floating gate has a first protruding structure at a sidewall extending along the first direction. A first insulating layer crosses over the floating gate and the trench isolation lines. A control gate line is disposed on the first insulating layer over the floating gate, extending along a second direction intersecting with the first direction. The control gate line has a second protruding structure correspondingly stacked over the first protruding structure of the floating gate, and crosses over the trench isolation lines.

A structure of memory device includes trench isolation lines in a substrate, extending along a first direction. An active region in the substrate is between adjacent two of the trench isolation lines. A dielectric layer is disposed on the active region of the substrate. A floating gate corresponding to a memory cell is disposed on the dielectric layer between adjacent two of the trench isolation lines. The floating gate has a first protruding structure at a sidewall extending along the first direction. A first insulating layer crosses over the floating gate and the trench isolation lines. A control gate line is disposed on the first insulating layer over the floating gate, extending along a second direction intersecting with the first direction. The control gate line has a second protruding structure correspondingly stacked over the first protruding structure of the floating gate.

Devices and methods for forming a device are presented. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second lower sub-gates of first and second transistors are formed in the cell area. A common upper sub-gate of the first and second transistors is formed. The common upper sub-gate and first and second lower sub-gates are separated by an intergate dielectric layer and the common upper sub-gate surrounds the first and second lower sub-gates.

Low cost high performance EEPROM device

Growing community of inventors

Singapore, Singapore

Qiuji Zhao