Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Semiconductor Manufacturing (shanghai) International Corporation

Semiconductor Manufacturing (beijing) International Corporation

Qiuhua Han

Xiaoying Meng

Haiyang Zhang

Qingtian Ma

Yi Huang

Yan Chen

Xinpeng Wang

Kai Yan

Duan Yi Wu

Longjuan Tang

Lihong Xiao

A method of manufacturing a semiconductor device includes providing a substrate structure, which includes a substrate, one or more semiconductor fins on the substrate, a gate structure on each fin, an active region located in said fins, and an interlayer dielectric layer covering at the active region. The method includes forming a hard mask layer over the interlayer dielectric layer and the gate structure, and using an etch process with a patterned etch mask, forming a first contact hole extending through the hard mask layer and extending into a portion of the interlayer dielectric layer, using patterned a mask. The method further includes forming a sidewall dielectric layer on sidewalls of the first contact hole, and using an etch process with the sidewall dielectric layer as an etch mask, etching the interlayer dielectric layer at bottom of the first contact hole to form a second contact hole extending to the active region.

Method of FinFET contact formation

The present disclosure teaches interconnection structures and methods for manufacturing the same. In one implementation, a method may include: providing a substrate structure, including: a substrate, an interlayer dielectric layer on the substrate, a plurality of first through holes running through the interlayer dielectric layer, and a first metal layer filling the plurality of first through holes; forming a through hole structural layer on the substrate structure, where a dual-damascene through hole structure included in the through hole structural layer includes: a second through hole and a third through hole in the through hole structural layer, and an opening on the second through hole and the third through hole, and a part of the through hole structural layer between the second through hole and the third through hole is exposed in the opening; filling a second metal layer in the second through hole and the third through hole, where an upper surface of the second metal layer is lower than an upper surface of the part of the through hole structural layer; etching the part of the through hole structural layer so that the upper surface of the part is lower than the upper surface of the second metal layer; and forming, in the opening, a third metal layer connected to the second metal layer. The present disclosure addresses a problem of a cauliflower defect in the prior art.

Interconnection structure and method for manufacturing same

A method is provided for fabricating stripe structures. The method includes providing a substrate; and forming a to-be-etched layer on the substrate. The method also includes forming a hard mask pattern having a first stripe on the to-be-etched layer; and forming a photoresist pattern having a stripe opening on the to-be-etched layer and the hard mask pattern having the first stripe. Further, the method includes forming a polymer layer on a top surface and side surfaces of the photoresist pattern to reduce a width of the stripe opening; forming hard mask patterns having a second stripe by etching the hard mask pattern having the first stripe using the photoresist pattern having the polymer layer as an etching mask; and forming the stripe structures by etching the to-be-etching layer using the hard mask pattern having the second stripe as an etching mask until the substrate is exposed.

Semiconductor device including stripe structures

Various embodiments provide a semiconductor structure having a common gate and fabrication method of the semiconductor structure. In an exemplary method, after forming a first metal gate and a second metal gate, a conductive material layer can be formed at least at the boundary between the first metal gate and the second metal gate. Thus, one end of the conductive material layer can be connected to a first metal gate electrode, and the other end of the conductive material layer can be connected to a second metal gate electrode. The resistance between the first metal gate electrode and the second metal gate electrode can be effectively reduced. Gate voltages of an NMOS transistor and a PMOS transistor of the common gate can be the same.

Semiconductor structure having common gate

The disclosed subject matter provides a p-channel metal-oxide-semiconductor (PMOS) and fabrication method thereof. The PMOS transistor is fabricated by a method including forming a dummy gate structure on a semiconductor substrate, forming a source region and a drain region in the semiconductor substrate on both sides of the dummy gate structure, forming an intermediate layer to cover the dummy gate structure and the semiconductor substrate, and forming a multiple-level etching stop layer including at least a first etching stop layer and a second etching stop layer. The fabrication method also includes performing a UV curing process after forming each of the first and second etching stop layers.

PMOS transistor and fabrication method thereof

A method is provided for fabricating transistors. The method includes providing a semiconductor substrate. The substrate has a gate film and a mask film formed on a top surface. The mask film contains implanted carbon ions. The method further includes forming a mask layer by etching the mask film and then forming a gate layer by etching through the gate film using the mask layer as a mask until the substrate is exposed. The method also includes forming a first sidewall containing implanted carbon ions on the side surface of the gate layer and the mask layer; forming a stress layer in the substrate on both sides of the gate layer and the first sidewall; and forming a source region on one side of the gate layer and the first sidewall and a drain region on the other side of the gate layer and the first side wall.

Semiconductor structures and fabrication method thereof

A method of fabricating a fin for a FinFET device includes providing a semiconductor substrate, forming a patterned silicon germanium layer on the semiconductor substrate, epitaxially growing a silicon layer on a top surface and sidewalls of the patterned silicon germanium layer, forming a sacrificial layer covering the patterned silicon germanium layer, and removing the sacrificial layer and a portion of the silicon layer disposed on the top surface of the patterned silicon germanium layer until a top surface of the sacrificial layer is co-planar with the top surface of the patterned silicon germanium layer. The method further includes removing the patterned silicon germanium layer and removing the sacrificial layer to form the fin. The epitaxially formed fin does not have the issues of line width roughness and edge roughness to improve the performance of the FinFET device.

Method of FinFET formation

Semiconductor devices and fabrication methods are provided. In an exemplary method, a semiconductor layer including a first opening can be provided. The first opening can be filled with a stress material. The stress material can then be etched to form a second opening having a width less than a width of the first opening to leave a stress material layer in the semiconductor layer and on each sidewall of the second opening. The semiconductor layer can be etched to form a fin structure on a sidewall surface of the stress material layer. A main gate structure can be formed on the sidewall surface of the fin structure. A back gate structure can be formed on the sidewall surface of the stress material layer.

Semiconductor device

Various embodiments provide FinFETs and methods for forming the same. In an exemplary method, a semiconductor substrate having sacrificial layers formed thereon is provided. First sidewall spacers and second sidewall spacers are sequentially formed on both sides of each sacrificial layer. The sacrificial layers can be removed. A first width is measured as a distance between adjacent first sidewall spacers, and a second width is measured as a distance between adjacent second sidewall spacers. When the first width is not equal to the second width, the first sidewall spacers or the second sidewall spacers are correspondingly etched such that the first width is equal to the second width. The semiconductor substrate is etched using the first sidewall spacers and the second sidewall spacers as an etch mask, to form fins, such that a top of each fin has a symmetrical morphology.

Fin field effect transistor and method for forming the same

A method of manufacturing a semiconductor device is provided. The method includes providing a semiconductor substrate, forming a plurality of fins on the semiconductor substrate, forming a plurality of shallow trench isolation (STI) structures on the semiconductor substrate on opposite sides of the fins, forming a dummy gate on the fins, forming gate spacers on opposite sides of the dummy gate, etching a first portion of the STI structures disposed outside a gate region, the first portion having a first predetermined thickness, forming an interlayer dielectric over the semiconductor substrate, removing the dummy gate, etching a second portion of the STI structures disposed in the gate region, the second portion having a second predetermined thickness, and forming a high-k dielectric layer and a metal gate in an area where the dummy gate is removed.

Semiconductor device and method of manufacturing the same

Stripe structures and fabrication method thereof

Semiconductor structure having common gate and fabrication method thereof

A method is provided for fabricating an MOS transistor. The method includes providing a semiconductor substrate; forming a metal gate structure; and forming a source region and a drain region. The method also includes forming a contact-etch-stop layer; forming an interlayer dielectric layer on the contact-etch-stop layer and the metal gate structure; and forming a first opening in the interlayer dielectric layer with a portion of the sidewall spacer and the contact-etch-stop layer left on the bottom. Further, forming a first contact hole in the interlayer dielectric layer by removing the portion of the sidewall spacer and the contact-etch-stop layer. Further, the method also includes forming a first conductive via in the first contact hole.

MOS transistors and fabrication method thereof

Semiconductor device and fabrication method

A semiconductor device and method of forming the same includes a substrate having a NMOS region and a PMOS region. The method includes forming a dummy gate structure having a stacked sacrificial dielectric layer and a sacrificial gate material layer on the NMOS and PMOS regions. The method further includes concurrently removing the stacked sacrificial dielectric layer and a sacrificial gate material layer to form a groove, and forming a high-K dielectric layer and a first metal gate layer in the grove. The method also includes forming a hard mask over the NMOS region, removing the first metal gate layer and the high-K dielectric layer in the PMOS region to form a channel groove, forming a second high-K dielectric layer and a second metal gate layer in the channel grove, and removing the hard mask. The work function metal layer in the NMOS and PMOS regions can be independently controlled.

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Shanghai, China

Qiuhua Han