International Business Machines Corporation

Globalfoundries Inc.

Renesas Electronics Corporation

Qiqing Christine Ouyang

Alexander Reznicek

Pranita Kerber

Jack Oon Chu

Dominic Joseph Schepis

Herbert Lei Ho

Meikei Ieong

Jeremy Daniel Schaub

Christopher D Sheraw

Mahender Kumar

Michael D Steigerwalt

Paul A Papworth

Xiangdong Chen

Steven John Koester

Jie Deng

Keith E Fogel

Tak H Ning

Dureseti Chidambarrao

Judson Robert Holt

Haizhou Yin

Kern Rim

Siddhartha Panda

Aaron K Baughman

Shikhar Kwatra

Stephen W Bedell

Guy M Cohen

Kevin K Chan

Alfred Grill

Andres Bryant

Geng Wang

Fei Liu

Kathryn Turner Schonenberg

Chun-Yung Sung

Thomas Safron Kanarsky

Yujun Li

Gary William Reiss

Gabriel Konrad Dehlinger

Jo Arao Ramos

Deepak Rangarao

Marcio T Moura

Edward J Nowak

David V Horak

Ning Li

Toshiharu Furukawa

Shogo Mochizuki

Charles W Koburger, Iii

Keith Kwong Hon Wong

Christian Lavoie

Paul Michael Solomon

Jeng-Bang Yau

Zhen Zhang

Robert H Dennard

Xiao Hu Liu

Jin Cai

John Albrecht Ott

Dae-Gyu Park

Huajie Chen

Xinhui Wang

Fadi Hikmat Gebara

Raghavasimhan Sreenivasan

Gen Tsutsui

Anthony Gene Domenicucci

Seshadri Subbanna

Anda C Mocuta

Kam-Leung Lee

Hung-Yang Chang

Yaocheng Liu

Thomas Ludwig

Lisa F Edge

Yajuan Wang

Kai Xiu

Massimo V Fischetti

Igor Khapov

Silke H Christianson

Meikei Leong

Mei-Kei Ieong

Aspects include processors configured to (or include program code that causes a processor to) provide for data classifier devices that extract from structured text business data inputs, via natural language understanding processing, training set data elements (for example, training keywords, training concepts, training entities, and/or training taxonomy classifications, etc.). The aspects identify associations within the structured training business data of each of a plurality of business class categories with respective ones of the extracted training set data elements; and build a logical relationship data classification training knowledge base ontology that connects ones of the business classes to respective associated ones of the extracted training data elements as questions, into a plurality of knowledge base ontology question-business class associations.

Data classification for data lake catalog

Data classification extracts from structured text business data inputs, via natural language understanding processing, training set data elements (training keywords, training concepts, training entities, and/or training taxonomy classifications). Embodiments identify associations within the structured training business data of business class categories with respective ones of extracted training set data elements, and build a logical relationship data classification training knowledge base ontology that connects business classes to respective associated ones of extracted training data elements as questions into knowledge base ontology question-business class associations.

An approach for altering alter training data and training process associated with a neural network to emulate environmental noise and operational instrument error by using the concepts of shots to sample within a squeezed space model, wherein shots are an uncertainty index that is the average of all shots from a sampling, is disclosed. The approach leverages a squeeze theorem to create a squeezed space model based on the regression of the upper and lower bound associated with the environmental noise and instrument error. The approach calculates an average noise index based on the squeezed space model, wherein the index is used to alter the training data and process.

Modeling environment noise for training neural networks

An approach alerting users based on a detected defect during manufacturing quality inspection based on graphical images is disclosed. The approach initiates a device inspection, wherein a model controller collects metadata about a product to be inspected and select a first model with a highest score to identify defects in the device. The approach utilizes an API to obtain results from the inspection and after determining that another model is available, initiating the second model run via an edge device performing the inspection of the device. And the algorithm awaits a response in detecting a defect during either the first model run or the second model run, providing an alert detailing the defect detected in the device.

Detection of defect in edge device manufacturing by artificial intelligence

A method, a computer system, and a computer program product for parallel conversion is provided. Embodiments of the present invention may include analyzing raw classical code using a code embedded deep learning model. Embodiments of the present invention may include analyzing running classical code using a deep learning model. Embodiments of the present invention may include marking a location of the raw classical code for a first quantum conversion. Embodiments of the present invention may include suggesting a memory size of the running classical code for a second quantum conversion. Embodiments of the present invention may include aggregating the raw classical code for the first quantum conversion. Embodiments of the present invention may include aggregating the running classical code for the second quantum conversion.

Classical artificial intelligence (AI) and probability based code infusion

Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.

Transistor structure with varied gate cross-sectional area

A method of making a semiconductor device includes forming a first silicon germanium layer on a substrate, the first silicon germanium layer forming a portion of a first transistor; forming a second silicon germanium layer on the substrate adjacent to the first silicon germanium layer, the second silicon germanium layer forming a portion of a second transistor and having a germanium content that is different than the first silicon germanium layer and a thickness that is substantially the same; growing by an epitaxial process a compressively strained silicon germanium layer on the first silicon germanium layer, and a tensile strained silicon germanium layer on the second silicon germanium layer; patterning a first fin in the compressively strained silicon germanium layer and the first silicon germanium layer; and patterning a second fin in the tensile strained silicon germanium layer and the second silicon germanium layer.

Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step

A semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The at least one semiconductor fin includes a channel region interposed between opposing source/drain regions. A gate stack is on the upper surface of the substrate and wraps around sidewalls and an upper surface of only the channel region. The channel region is a dual channel region including a buried channel portion and a surface channel portion that completely surrounds the buried channel.

Semiconductor device including epitaxially formed buried channel region

A semiconductor device and a method for fabricating the device. The method includes: providing a FinFET having a source/drain region, at least one SiGe fin, a silicon substrate, a local oxide layer is formed on the silicon substrate, a gate structure is formed on the at least one SiGe fin and the local oxide layer, the gate structure is encapsulated by a gate hard mask and sidewall spacer layers; recessing the at least one SiGe fin in the source/drain region to the sidewall spacer layers and the silicon substrate layer; recessing the local oxide layer in the source/drain region to the sidewall spacer layer and the silicon substrate; growing a n-doped silicon layer on the silicon substrate; growing a p-doped silicon layer or p-doped SiGe layer on the n-doped silicon layer; and forming a silicide layer on the p-doped silicon layer or p-doped SiGe layer.

SiGe FinFET with improved junction doping control

A metal-oxide-semiconductor field effect transistor (MOSFET) and a method of fabricating a MOSFET are described. The method includes depositing and patterning a dummy gate stack above an active channel layer formed on a base. The method also includes selectively etching the active channel layer leaving a remaining active channel layer, and epitaxially growing silicon doped active channel material adjacent to the remaining active channel layer.

Reduced resistance short-channel InGaAs planar MOSFET

A method of manufacturing a semiconductor device includes forming a plurality of fin structures on a substrate, the plurality of fin structures including a diffusion region, forming an epitaxial layer on the plurality of fin structures in an area of the diffusion region such that a height of the upper surface of the epitaxial layer over plurality of fin structures is substantially equal to the height of the upper surface of the epitaxial layer between the plurality of fin structures, and planarizing the upper surface of the epitaxial layer by one of etch back and reflow annealing.

Semiconductor device and method of manufacturing the semiconductor device

A method of forming a semiconductor device that includes forming a fin structure from a semiconductor substrate, and forming a gate structure on a channel region portion of the fin structure. A source region and a drain region are formed on a source region portion and a drain region portion of the fin structure on opposing sides of the channel portion of the fin structure. At least one sidewall of the source region portion and the drain region portion of the fin structure is exposed. A metal semiconductor alloy is formed on the at least one sidewall of the source region portion and the drain region portion of the fin structure that is exposed.

FinFET device with vertical silicide on recessed source/drain epitaxy regions

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Yorktown Heights, NY, United States of America

Qiqing Christine Ouyang