Nxp B.v.

Verb Surgical Inc.

Qiong Wu

Kevin Mahooti

Klaus R Zietlow

Koray Sahin

Philip L Graves

Jonathan Bernard

Roth K Wiedrick

Peter Christiaans

Robert Glenn Il Crosby

Qinghai Hu

A robotic surgical system is disclosed having a ring network for communicating information between a controller and nodes of one or more robotic arms. A communications protocol is described by which synchronous and asynchronous information can be communicated to and from the nodes of the robotic arms. Also disclosed are various aspects of a physical layer that can be used with the network.

Robotic surgical system having a communication network of a ring topology and method for use therewith

A proximal end portion of a robotic surgical arm is to be coupled to an adapter of a surgical robotic platform, for use during a surgical session at the platform, and then decoupled from the adapter for storage until being re-coupled for use during another surgical session at the platform. A resonant-mode transformer-coupled power converter is provided that has a secondary side and a primary side. The secondary side is in the arm and has a transformer secondary coil in the proximal end portion of the arm. The primary side has a transformer primary coil in the adapter. The primary and secondary coils are held at positions and orientations that enable mutual inductive coupling between them for operation of the power converter when the arm is coupled to the adapter. Other embodiments are also described and claimed.

Surgical robotic arm with wireless power supply interface

A wireless charging receiver operates on a resonance principle and includes an impedance matching circuit coupled between an antenna and a rectifier circuit. The impedance matching circuit has both series-connected and parallel-connected capacitors. At least one of the capacitors is a tunable variable capacitor. A method is provided for automatically adjusting a capacitance value of the at least one variable capacitor based on an error voltage between a target rectifier voltage and a measured rectifier voltage. Automatically adjusting the antenna impedance of the receiver provides for improved power transfer efficiency for changing operating conditions. In one embodiment, one or more of the parallel-connected capacitors are variable capacitors. In another embodiment, one or more of the series-connected capacitors are variable capacitors.

Automatic tuning of resonance-based wireless charging receiver

A method and apparatus for correcting the offset and linearity error of a data acquisition system. A charge redistribution digital to analog convertor (CDAC) is connected to one of the differential inputs of a comparator whose second input comes from a function CDAC. The calibration algorithm is built into a digital control unit. The digital control unit detects the offset and capacitor mismatch errors sequentially, stores the calibration codes for each error in calibration mode and provides the input-dependent error correction signals synchronized with the binary search timing to adjust the differential input of the comparator and compensate the input-dependent errors present at the output of the non-ideal function CDAC during normal conversions.

Input-independent self-calibration method and apparatus for successive approximation analog-to-digital converter with charge-redistribution digital to analog converter

An apparatus implements analog-to-digital conversion with released requirement on the reference settling errors and improved immunity to the noise originated from the power supply, ground and the positive and negative references. It includes a comparator comparing the specified reference levels with the analog input, multi DAC sub-circuits with separate non-binary search schemes applied to and a digital control logic controlling the reference search process. No cross-talk occurs among the different non-binary search algorithms. Each redundancy scheme is localized in a respective DAC sub-circuit and covers the reference levels only in the current DAC. The non-binary search algorithms are fulfilled in the digital domain and trade the non-binary search step sizes with the number of the search steps to introduce redundancy to the reference levels.

Successive approximation register analog to digital converter

An analog sample-and-hold switch has parallel branches extending from an input node to an output node connected to a hold capacitor, each branch having a PMOS signal switch FET in series with a PMOS dummy FET. A sample clock controls on-off switching of the PMOS signal switch FETs, and an inverse of the sample clock controls a complementary on-off switching of the PMOS dummy FETs. A bias sequencer circuit biases the PMOS signal switch FETs and biases the PMOS dummy FETs, in a complementary manner, synchronous with their respective on-off states. The on-off switching of the PMOS dummy FETs injects charge cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs.

Switch-body PMOS switch with switch-body dummies

A sample-and-hold feed switch has parallel PMOS branches and parallel NMOS branches, each extending from an input node to an output node connected to a hold capacitor. Each PMOS branch has a PMOS switch FET connected to a matching PMOS dummy FET, and each NMOS branch has an NMOS switch FET connected to a matching NMOS dummy FET. A sample clock switches the PMOS switch FETs on and off, and a synchronous inverse sample clock effects complementary on-off switching of the PMOS dummy FETs. Concurrently, a synchronous inverse sample clock switches the NMOS switch FETs on and off, and the sample clock effects a complementary on-off switching of the NMOS dummy FETs. A bias sequencer circuit biases the bodies of the PMOS switch FETs and the bodies of the PMOS dummy FETs, in a complementary manner, and biases the NMOS switch FETs and the NMOS dummy FETs, also in a complementary manner. The on-off switching of the PMOS dummy FETs injects charge, cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs. The on-off switching of the NMOS dummy FETs injects charge that cancels a charge injection by the NMOS signal switch FETs, and injects glitches that cancels glitches injected by the NMOS signal switch FETs.

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San Jose, CA, United States of America

Qiong Wu