Lsi Logic Corporation

Qiong J Yu

Bo Shen

Alexander Y Tetelbaum

Prasad Subbarao

Radoslav Ratchkov

Charutosh Dixit

Thomas Mathews Antisseril

Julie Beatty

Alexander Tetelbuam

A method for checking power errors in an ASIC design is disclosed. The method includes providing a power checker software program with one or more power checker modules that each check a particular type of power element in the ASIC design. A power checker database is created that stores the following: individual power elements in the ASIC design, a connectivity graph of the power elements, and location bins corresponding to physical areas in ASIC design that identify the power elements that are located within each area. The method further includes providing a user with a choice of which power elements in the design to check, and executing the power checker modules corresponding to the selected power elements in order to check for errors in the selected power elements. Finally, any detected errors are output for the user.

Method and system for checking for power errors in ASIC designs

A method of datapath cell placement is disclosed that minimizes signal propagation time through a datapath macro and datapath macro area that includes the steps of receiving as input a datapath description for a datapath block wherein the datapath description describes at least one of a plurality of datapath cells, a plurality of data input pins, a plurality of data output pins, and a plurality of control signal pins; sorting the plurality of data input pins and the plurality of data output pins according to a hierarchy of sorting criteria; determining a plurality of corresponding criticality values for the plurality of datapath cells; sorting the plurality of datapath cells according to the plurality of corresponding criticality values; assigning the plurality of datapath cells to a plurality of corresponding columns; and arranging the plurality of datapath cells within at least one of the plurality of corresponding columns to minimize signal propagation delay through the datapath block.

Method of datapath cell placement for bitwise and non-bitwise integrated circuit designs

A method of datapath cell placement is disclosed that minimizes signal propagation time through a datapath macro and datapath macro area that includes the steps of receiving a datapath description of constrained input pins, unconstrained input pins, and output pins for a datapath block; assigning a first corresponding first cell level to a first datapath cell in a data path of a constrained input pin wherein the first corresponding first cell level is representative of a number of intervening datapath cells between the first datapath cell and the constrained input pin; assigning a second corresponding first cell level to a second datapath cell in a data path connecting the first datapath cell to an unconstrained input pin that is substantially identical to the first corresponding first cell level; and assigning a corresponding second cell level to the datapath cell in the data path connecting the first datapath cell to the unconstrained input pin wherein the second cell level is representative of a number of intervening datapath cells between the datapath cell in the data path of the unconstrained input pin and the unconstrained input pin.

Method of datapath cell placement for an integrated circuit

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San Jose, CA, United States of America

Qiong J Yu