Broadcom Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Qintao Zhang

Akira Ito

Shom Ponoth

Mei Xue

Aimin Xing

Wenwei Yang

A one-time programmable memory (OTP) is provided that includes a combined word line programming line (WL-PL). The OTP includes a programmable transistor having a first threshold voltage and a first breakdown voltage, and a pass transistor having a second threshold voltage and a second breakdown voltage. The combined WL-PL is electrically connected to respective gate electrodes of both the programmable transistor and the pass transistor so that both receive the same control voltage. The second gate electrode has a work function that is greater than that of the first gate electrode, so that the second gate breakdown voltage is greater than the first gate breakdown voltage, which enables the use of the combined WL-PL.

One time programmable memory with a twin gate structure

A programmable cell includes a split gate structure. The split gate structure includes a thin gate dielectric region and a thick gate dielectric region disposed below a gate conductor. A thickness of the thick oxide region is more than a thickness of the thin oxide region. The programmable cell can be fabricated using angle doping to dope an area associated with the thin dielectric region.

Method of making a programmable cell and structure thereof

Methods of fabricating devices (e.g., FDSOI devices) having multiple threshold voltages are described. One method includes providing a first fixed charge region proximate to an interface of an insulating (e.g., buried oxide (BOX) layer) and a semiconductor substrate for a first device. The first charge region has a first configuration of fixed charges. The method also includes providing a second fixed charge region proximate to the interface of the insulating layer and the semiconductor substrate for the second device. The second charge region has a second configuration of fixed charges that is different than the first configuration.

Devices having multiple threshold voltages and method of fabricating such devices

A fin-shaped field-effect transistor (finFET) device is provided. The finFET device includes a substrate material with a top surface and a bottom surface. The finFET device also includes a well region formed in the substrate material. The well region may include a first type of dopant. The finFET device also includes a fin structure disposed on the top surface of the substrate material. A portion of the fin structure may include the first type of dopant. The finFET device also includes an oxide material disposed on the top surface of the substrate material and adjacent to the portion of the fin structure. The finFET device also includes a first epitaxial material disposed over a portion of the fin structure. The first epitaxial material may include a second type of dopant.

Super junction LDMOS finFET devices

An MOS device with increased drain-source voltage (Vds) includes a source region and a drain region deposited on a substrate. A gate region includes an inner spacer that extends the drain region. The inner spacer is formed attached to an isolation spacer that isolates the drain region from the gate region. The inner spacer is configured to extend the drain region to modify an electric field in a portion of a conductive band of the MOS device.

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Tustin, CA, United States of America

Qintao Zhang