International Business Machines Corporation

Applied Materials, Inc.

Samsung Electronics Co., Ltd.

Globalfoundries Inc.

Varian Semiconductor Equipment Associates, Inc.

Qintao Zhang

Kangguo Cheng

Juntao Li

Geng Wang

Wei Zou

Samphy Hong

Sipeng Gu

David Jon Lee

Kyu-Ha Shim

Jun-Feng Lu

Hans-Joachim Ludwig Gossmann

Baonian Guo

Lei Zhong

Felix Levitov

Dechao Guo

Xinhui Wang

Rajesh Prasad

Liyang Song

Scott Falk

Kyuha Shim

Jason Appell

John J Hautala

Yi Zheng

Myung-Hee Na

Seong-Dong Kim

Thomas A Wallner

Aseem Kumar Srivastava

Jin Zheng Wallner

Supakit Charnvanichborikarn

William R Bogiages, Jr

David P Surdock

Wei Zhao

Carlos Caballero

Wayne R Swart

Jian Kang

Judy Campbell Soukup

Vittoriano Ruscio

Ting Cai

Durgaprasad Chaturvedula

Weiye He

Ma Ning

Aldrin Bernard Vincent Eddy

Jeffrey P Koch

Avishay Vaxman

Daniel G Deyo

Disclosed herein are approaches for forming contacts in a 4Fvertical dynamic random-access memory device. One method includes providing a plurality of fins extending from a substrate, forming a spacer layer over the plurality of fins, and etching the substrate to expose a base portion of the plurality of fins. The method may include forming a doped layer along the base portion of the plurality of fins and along an upper surface of the substrate, and forming an oxide spacer over the doped layer.

Bottom contact formation for 4Fvertical DRAM

Disclosed herein are approaches for forming a shallow trench isolation (STI) to improve extremely thin silicon on insulator (ETSOI) device performance. In one approach, a method may include providing a device stack comprising a buried oxide (BOX) layer in a substrate, patterning a hardmask over the substrate, and forming a plurality of isolation regions in the device stack, wherein the plurality of isolation regions extend through the box layer and the substrate. The method may further include forming a well mask over the device stack, wherein an opening through the well mask exposes a first isolation region of the plurality of isolation regions, and modifying a stress of a material of the first isolation region by implanting the first isolation region of the plurality of isolation regions.

Selective implantation into STI of ETSOI device

A camera may capture reflected light from the surface of the wafer during a semiconductor process that adds or removes material from the wafer, such as an etch process. To accurately determine an endpoint for the process, a camera sampling rate and light source intensity may be optimized in the process recipe. Optimizing the light source intensity may include characterizing light intensities that will be reflected from the waiver using an image of the wafer. Pixel intensities may be used to adjust the light source intensity to compensate for more complex wafer patterns. Optimizing the camera sampling rates may include nondestructively rotating a view of the wafer and converting the sampled intensities to the frequency domain. The camera sampling rate may be increased or decreased to remove spatial noise from the image without oversampling unnecessarily. These optimized parameters may then generate a clean, repeatable trace for endpoint determination.

Endpoint optimization for semiconductor processes

Disclosed herein are approaches for forming contacts in a 4Fvertical dynamic random-access memory device. One method includes forming a hardmask over a plurality of pillars and over a plurality of anchors, wherein the pillars are separated from one another by a STI, and removing the STI and etching through the hardmask to form a plurality of gate trenches. The method may further include delivering a capping material to the pillars at a non-zero angle relative to a perpendicular extending from an upper surface of the pillars, wherein the capping material forms a capping layer along an upper portion of the pillars without forming the capping layer along a lower portion of the pillars. The method may further include etching the pillars to trim the lower portion of the pillars, and forming a plurality of contacts in the upper portion of the pillars.

Vertical FinFet formation using directional deposition

A method of forming a semiconductor device may include forming a plurality of fins extending from a buried oxide layer, wherein a masking layer is disposed atop each of the plurality of fins, and performing a high-temperature ion implant to the semiconductor device. The method may further include performing an etch process to remove the masking layer from atop each of the plurality of fins, wherein the etch process does not remove the buried oxide layer.

Etch rate modulation of FinFET through high-temperature ion implantation

Disclosed herein are methods for increasing MOSFET threshold voltage to enable higher SiC mobility. In some embodiments, a method includes providing a device structure including a dielectric layer over an epitaxial layer, patterning a hardmask layer over the dielectric layer, performing a first ion implant to form a well in the epitaxial layer, and performing a second ion implant to form an interface layer between the well and the dielectric layer.

Ion implantation to increase MOSFET threshold voltage

Methods may include providing a device structure having a shielding layer formed beneath each trench in a MOSFET to protect trench corner breakdown. The method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. The method may further include forming a shielding layer in the device structure by directing ions into the plurality of trenches.

MOSFET gate shielding using an angled implant

Disclosed herein are methods for forming a buried layer using a low-temperature ion implant. In some embodiments a method may include providing an opening through a mask, wherein the mask is formed directly atop a substrate, and forming a buried layer in the substrate by performing a low-temperature ion implant through the opening of the mask. The method may further include forming an oxide layer over the substrate including over the buried layer.

Low-temperature implant for buried layer formation

Disclosed herein are methods for backside wafer dopant activation using a low-temperature ion implant. In some embodiments, a method may include forming a semiconductor device atop a first main side of a substrate, and performing a low-temperature ion implant to a second main side of the substrate, wherein the first main side of the substrate is opposite the second main side of the substrate. The method may further include performing a second ion implant to the second main side of the substrate to form a collector layer.

Backside wafer dopant activation

Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

Ion implantation to reduce nanosheet gate length variation

Provided here are methods and manufacturing systems to implant protons into SiC IGBT devices at multiple depths in the drift layer of the SiC IGBT device. Provides are SiC IGBT devices manufactured with process steps including multiple proton implant processes where the SiC IGBT device is irradiated with ion to affect proton implantation into the SiC IGBT device at multiple depths in the drift region to reduced minority carrier lifetime.

Minority carrier lifetime reduction for SiC IGBT devices

A method of promoting adhesion between a dielectric layer of a semiconductor device and a metal fill deposited within a trench in the dielectric layer, including performing an ion implantation process wherein an ion beam formed of an ionized dopant species is directed into the trench at an acute angle relative to a top surface of the dielectric layer to form an implantation layer in a sidewall of the trench, and depositing a metal fill in the trench atop an underlying bottom metal layer, wherein the metal fill adheres to the sidewall.

Method for BEOL metal to dielectric adhesion

Disclosed herein are approaches for reducing buried channel recess depth using a non-doping ion implant prior to formation of the buried channel. In one approach, a method may include providing an oxide layer over a substrate, performing a non-doping implantation process through the oxide layer to form an amorphous region in the substrate, and forming a photoresist over the oxide layer. The method may further include forming a buried layer in the substrate by implanting the substrate through an opening in the photoresist, and performing an oxidation and dopant drive-in process to the amorphous region and to the buried layer to form a second oxide layer.

Methods for forming N-type buried layer in a substrate by performing non-doping implant through oxide layer formed over the substrate

A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.

Vertical field effect transistor including integrated antifuse

A method may include providing a substrate, where the substrate includes a first main surface and a second main surface, opposite the first main surface. The second main surface may include a stress compensation layer. The method may include directing ions to the stress compensation layer in an ion implant procedure. The ion implant procedure may include exposing a first region of the stress compensation layer to a first implant process, wherein a second region of the stress compensation layer is not exposed to the first implant process.

Techniques and apparatus for anisotropic stress compensation in substrates using ion implantation

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Mt. Kisco, NY, United States of America

Qintao Zhang