Enthone Incorporated

Other

Qingyun Chen

Richard W Hurtubise

Vincent Paneccasio, Jr

Christian Witt

Charles Valverde

Xuan Lin

Daniel Stritch

Nicolai Petrov

Eric Yakobson

Joseph Anthony Abys

A method and composition for metallizing a via feature in a semiconductor integrated circuit device substrate, using a leveler compound which is a dipyridyl compound.

Method and composition for electrodeposition of copper in microelectronics with dipyridyl-based levelers

A method for metallizing a via feature in a semiconductor integrated circuit device substrate, wherein the semiconductor integrated circuit device substrate comprises a front surface, a back surface, and the via feature and wherein the via feature comprises an opening in the front surface of the substrate, a sidewall extending from the front surface of the substrate inward, and a bottom. The method comprises contacting the semiconductor integrated circuit device substrate with an electrolytic copper deposition chemistry comprising (a) a source of copper ions and (b) a leveler compound, wherein the leveler compound is a reaction product of a dipyridyl compound and an alkylating agent; and supplying electrical current to the electrolytic deposition chemistry to deposit copper metal onto the bottom and sidewall of the via feature, thereby yielding a copper filled via feature.

A method is disclosed for metallizing a substrate comprising an interconnect feature in the manufacture of a microelectronic device, wherein the interconnect feature comprises a bottom, a sidewall, and a top opening having a diameter, D. The method comprises the following steps: depositing a barrier layer on the bottom and the sidewall of the interconnect feature, the barrier layer comprising a metal selected from the group consisting of ruthenium, tungsten, tantalum, titanium, iridium, rhodium, and combinations thereof; contacting the substrate comprising the interconnect feature comprising the bottom and sidewall having the barrier layer thereon with an aqueous composition comprising a reducing agent and a surfactant; and depositing copper metal onto the bottom and the sidewall of the interconnect feature having the barrier layer thereon.

Surface preparation process for damascene copper deposition

A method for plating copper onto a semiconductor integrated circuit device substrate by forming an initial metal deposit in the feature which has a profile comprising metal on the bottom of the feature and a segment of the sidewalls having essentially no metal thereon, electrolessly depositing copper onto the initial metal deposit to fill the feature with copper. A method for plating copper onto a semiconductor integrated circuit device substrate by forming a deposit comprising a copper wettable metal in the feature, forming a copper-based deposit on the top-field surface, and depositing copper onto the deposit comprising the copper wettable metal to fill the feature with copper.

Copper deposition for filling features in manufacture of microelectronic devices

A method of preparing an aqueous electroless deposition composition for electrolessly depositing Co or a Co alloy onto a substrate in manufacture of microelectronic devices by treating water or an aqueous electroless deposition composition with a deoxygenating treatment to reduce the oxygen concentration.

Manufacture of electroless cobalt deposition compositions for microelectronics applications

Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions.

Defectivity and process control of electroless deposition in microelectronics applications

A multilayer metal cap over a metal-filled interconnect feature in a dielectric layer for incorporation into a multilayer integrated circuit device, and a method for forming the cap.

Capping of metal interconnects in integrated circuit electronic devices

An electroless plating method and composition for depositing Co, Ni, or alloys thereof onto a metal-based substrate in manufacture of microelectronic devices, involving a source of deposition ions selected from the group consisting of Co ions and Ni ions, a reducing agent for reducing the depositions ions to metal onto the substrate, and a hydrazine-based leveling agent.

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Branford, CT, United States of America

Qingyun Chen