National Semiconductor Corporation

Qingping Zheng

Xin Yu Liu

Min Du

Vijaya G Ceekala

Peter Shing

Chandrakumar R Pathi

John Goldie

Interface circuitry and method for transmitting and receiving downstream and upstream data signals simultaneously via a common conductor pair. The composite signal containing the downstream and upstream data signal components being conveyed by the common conductor pair is isolated, e.g., via signal filtering or buffering, and combined with an appropriately scaled inverse replica of the outgoing upstream data signal to subtract out upstream data signal components and thereby provide the downstream data signal substantially free of any upstream data signal components.

Data signal transceiver circuitry for providing simultaneous bi-directional communication via a common conductor pair

A time shared bi-directional serial signaling system providing a differential signal with apparent duplex signal operation for higher and lower bandwidth data signals in a forward direction and another lower bandwidth data signal in a return direction.

Time shared bi-directional serial signaling system

A driver arrangement for a display includes at least one driver, such as a column driver, and a delay line arrangement coupled to the driver. The delay line arrangement delays a data signal provided to the driver by a delay period selectable from a plurality of possible delay periods. The delay line arrangement includes a calibration module that, when requested, is configured and arranged to adjust a current delay period produced by the delay line arrangement towards a predetermined delay period. Displays can include the driver arrangement to provide self-calibration of the delay line.

Methods and displays having a self-calibrating delay line

A circuit for pre-emphasis in data serialization. The circuit has a signal delayline to incrementally delay a serialized signal, producing a delayed serialized signal. The circuit has a one bit generator circuit, which determines the interval between receipt of one bit and a second bit. The one bit generator circuit has a strobe delayline to incrementally delay a strobe signal, producing a delayed strobe signal, a logical gate to compare the delayed strobe signal with a second strobe signal, and a logical component to determine how long the delayed strobe signal was delayed before it matched the second strobe signal. The circuit also has a comparison gate to detect transition points in the serialized signal by comparing the delayed serialized signal with the serialized signal. The circuit also has a current source to provide increased current for the serialized signal at the detected transition points.

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Saratoga, CA, United States of America

Qingping Zheng