Intel Corporation

Qinglei Zhang

Yueli Liu

Amanda E Schuckman

Rui Zhang

Stefanie M Lotz

Sri Ranga Sai Boyapati

Chong Zhang

Tao Wu

Islam A Salama

Mark S Hlad

Charavana K Gurumurthy

Sri Ranga Boyapati

Nikhil Sharma

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Bridge interconnection with layered interconnect structures

Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first surface finish on one or more electrical routing features located on a first side of a package substrate and on one or more lands located on a second side of the package substrate, the second side being opposite the first side of the substrate. The method may further include removing the first surface finish on the first side of the package substrate; and depositing a second surface finish on the one or more electrical routing features of the first side. The depositing of the second surface finish may be accomplished by one of a Direct Immersion Gold (DIG) process or an Organic Solderability Preservative (OSP) process. Other embodiments may be described and/or claimed.

Integrated circuit package substrate

Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.

In embodiments, a package assembly may include a die coupled with one or more conductive pads. A barrier layer may be directly coupled with and between the die and one or more of the conductive pads. The package assembly may further include a solder resist layer coupled with the die and the conductive pads, and one or more interconnects positioned at least partially within the solder resist layer and directly coupled with one or more of the conductive pads.

Low z-height package assembly

Embodiments of the present disclosure are directed towards coreless substrates with passive device pads, as well as methods for forming coreless substrates with passive device pads and package assemblies and systems incorporating such coreless substrates. A coreless substrate may comprise a plurality of build-up layers, such as bumpless build-up layers (BBUL). In various embodiments, electrical routing features and passive device pads may be disposed on an outer surface of the substrate. In various embodiments, the passive device pads may be coupled with a conductive element disposed on or within the build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power between the passive device pads and a die coupled to the coreless substrate.

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Chandler, AZ, United States of America

Qinglei Zhang