Altera Corporation

Qingjin Du

Tad Kwasniewski

Jingcheng Zhuang

Rakesh H Patel

Circuitry and methods for supporting serial communications over serial interconnects between circuit modules are provided. A data recovery circuit receives incoming serial data from the serial interconnect path with zero delay. The data recovery circuit includes a data sampler that samples the incoming serial data using a multiphase clock. Data samples are provided to a multiplexer that selects an optimum sampled data signal to use as a recovered data signal. The multiplexer has a control input that receives a phase pointer signal. Control circuitry in the data recovery circuit analyzes the sampled data signals and a current value of the phase pointer to compute a clock phase shift error. If the clock phase shift error exceeds a predetermined value, the phase pointer signal can be updated. The data recovery circuit may be implemented using hardwired circuitry or programmable logic.

Zero-delay serial communications circuitry for serial interconnects

Frequency synthesizer circuitry employs a delay line. A reference clock signal propagates through successive stages of the delay line, and the currents drawn by output buffers of all of the stages are added at a common node. The common node current is converted to a voltage, which is AC-coupled to an output buffer ring oscillator of the frequency synthesizer. The output buffer ring oscillator includes a plurality of inverters connected in a series. A feedback connection including a resistor is provided from an output node of the last inverter to an input node of the first inverter.

Frequency synthesizer circuitry employing delay line

A digital loop circuit&#x2014;i.e., a phase-locked loop ('PLL') or delay-locked loop ('DLL')&#x2014;having a simplified digital loop filter, is particularly well-suited for a programmable logic device (&#x201c;PLD&#x201d;). The loop filter may be a memory (e.g., a shift register) which counts the early/late or up/down signals from a phase detector or phase-frequency detector (&#x201c;error detector&#x201d;) and outputs a signal when the count exceeds a threshold. Separate integral and proportional paths of the loop may include chained shift registers, with each outputting a signal only when the previous shift register overflows into it. A digital error detector may respond nonlinearly, with outputs of different bit widths, to different amounts of phase or frequency error.

Digital loop circuit for programmable logic device

Variable capacitance circuitry includes a fine tuning bank and a medium tuning bank. The fine tuning bank includes a plurality of varactors of progressively increasing size (e.g., width). Only one of these varactors is turned on at any one time. The medium tuning bank includes a plurality of similarly sized varactor circuits. These are turned on selectively in thermometer fashion (e.g., more are turned on (or off) as more (or less) overall capacitance is needed). The medium tuning bank increment is matched to the fine tuning bank range, so that when the fine tuning bank reaches an end of its range, another medium increment can be added or subtracted while the fine tuning bank is reset to the other end of its range. A uniform progression of small, incremental, capacitance changes is therefore provided over the relatively wide tuning range of the medium bank.

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Dallas, TX, United States of America

Qingjin Du