Lawrence Livermore National Security, LLC

University of California

Other

Qinghui Shao

Lars F Voss

Rebecca J Nikolic

Adam M Conway

Sara Elizabeth Harrison

Clint Frye

Roger A Henderson

Mark A Stoyer

John Winter Murphy

Dongxia Qu

Srabanti Chowdhury

Charles E Hunt

Mihail Bora

Robert T Graff

Chin Li Cheung

Ishwara B Bhat

Erik Lars Swanberg, Jr

David Lawrence Hall

Catherine E Reinhardt

Cedric Rocha Leao

Daniel Heineck

Daniel Max Dryden

Mushtaq A Dar

Victor P Karpenko

Tzu Fang Wang

Dawn A Shaughnessy

Adam P Conway

Philip Datte

Clement Antoine Trosseille

An apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a first semiconductor material, an array of three dimensional (3D) structures above the substrate, a sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure, and an isolation region positioned between the 3D structures. Each 3D structure includes the first semiconductor material. The sidewall heterojunction layer includes a second semiconductor material, where the first and second semiconductor material have different bandgaps.

Three dimensional vertically structured electronic devices

Devices, systems and methods for solid-state X-ray detection with high temporal resolution are described. An example method includes receiving an X-ray pulse in a semiconductor chip resulting in an electron cloud being formed in the semiconductor chip, applying a first set of voltages across a first plurality of drift cathode strips on a first side of the semiconductor chip and a second plurality of drift cathode strips on a second side of the semiconductor chip, applying a second set of voltages to across the first and the second plurality of drift cathode strips to form an electric field having a linear profile to cause the electron cloud to drift along the middle of the semiconductor chip, and activating a counter cathode on the second side and one or more readout anodes on the first side to collect the electron cloud after spreading in the middle section of the semiconductor chip.

High temporal resolution solid-state X-ray detection system

In one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of three dimensional (3D) structures above the substrate, a gate region, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure. The gate region is present on a portion of an upper surface of the second region and the gate region is coupled to a portion of the at least one vertical sidewall of each 3D structure.

According to one embodiment, a device includes a first electrode, a second electrode spaced from the first electrode, a well extending between the first electrode and the second electrode, one or more chalcogens in the well, and at least one halogen mixed with the one or more chalcogens in the well. In addition, the chalcogens are selected from the group consisting of sulfur, selenium, tellurium, and polonium.

Liquid semiconductor-halogen based electronics

According to one embodiment, a method includes performing a plasma etching process on a masked III-V semiconductor, and forming a passivation layer on etched portions of the III-V semiconductor. The passivation layer includes at least one of a group III element and/or a metal from the following: Ni, Cr, W, Mo, Pt, Pd, Mg, Ti, Zr, Hf, Y, Ta, and Sc.

Metal-based passivation-assisted plasma etching of III-v semiconductors

In one embodiment, a method of forming a vertical transistor includes forming a layer comprising a semiconductor material above a substrate, defining three dimensional (3D) structures in the layer, forming a second region in at least one vertical sidewall of each 3D structure, and forming an isolation region between the 3D structures. In another embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of 3D structures above the substrate, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure.

According to one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a semiconductor material; an array of three dimensional (3D) structures above the substrate; and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, where the second region includes a portion of at least one vertical sidewall of the 3D structure.

In one embodiment, a product includes a structure comprising a material of a Group-III-nitride having a dopant, where a concentration of the dopant in the structure has a concentration gradient characteristic of diffusion of the dopant inward from at least a portion of a surface of the structure in a direction substantially normal to the portion of the surface. The structure has less than 1% decomposition of the Group-III-nitride at the surface of the structure.

Gallidation assisted impurity doping

According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.

Three dimensional vertically structured MISFET/MESFET

According to one embodiment, a product includes an array of three dimensional structures, where each of the three dimensional structure includes a semiconductor material; a cavity region between each of the three dimensional structures; and a first material in contact with at least one surface of each of the three dimensional structures, where the first material is configured to provide high energy particle and/or ray emissions.

Three dimensional radioisotope battery and methods of making the same

According to one embodiment, a product includes an array of three dimensional structures, a cavity region between each of the three dimensional structures, and a first material in contact with at least one surface of each of the three dimensional structures. In addition, each of the three dimensional structures includes a semiconductor material, where at least one dimension of each of the three dimensional structures is in a range of about 0.5 microns to about 10 microns. Moreover, the first material is configured to provide high energy particle and/or ray emissions.

Radiation tolerant microstructured three dimensional semiconductor structure

In one embodiment, an apparatus includes: a first layer including a n+ dopant or p+ dopant; an intrinsic layer formed above the first layer, the intrinsic layer including a planar portion and pillars extending above the planar portion, cavity regions being defined between the pillars; and a second layer deposited on a periphery of the pillars thereby forming coated pillars, the second layer being substantially absent on the planar portion of the intrinsic layer between the coated pillars. The second layer includes an n+ dopant when the first layer includes a p+ dopant. The second layer includes a p+ dopant when the first layer includes an n+ dopant. The apparatus includes a neutron sensitive material deposited between the coated pillars and above the planar portion of the intrinsic layer. In additional embodiments, an upper portion of each of the pillars includes a same type of dopant as the second layer.

Capacitance reduction for pillar structured devices

In one embodiment, an apparatus includes a three dimensional structure comprising a semiconductor material, and at least one thin film in contact with at least one exterior surface of the three dimensional structure for inducing a strain in the structure, the thin film being characterized as providing at least one of: an induced strain of at least 0.05%, and an induced strain in at least 5% of a volume of the three dimensional structure. In another embodiment, a method includes forming a three dimensional structure comprising a semiconductor material, and depositing at least one thin film on at least one surface of the three dimensional structure for inducing a strain in the structure, the thin film being characterized as providing at least one of: an induced strain of at least 0.05%, and an induced strain in at least 5% of a volume of the structure.

Three dimensional strained semiconductors

According to one embodiment, an apparatus for detecting neutrons includes an array of pillars, wherein each of the pillars comprises a rounded cross sectional shape where the cross section is taken perpendicular to a longitudinal axis of the respective pillar, a cavity region between each of the pillars, and a neutron sensitive material located in each cavity region.

Stress reduction for pillar filled structures

Methods for manufacturing solid-state thermal neutron detectors with simultaneous high thermal neutron detection efficiency (&#x3e;50%) and neutron to gamma discrimination (&#x3e;10) are provided. A structure is provided that includes a p+ region on a first side of an intrinsic region and an n+ region on a second side of the intrinsic region. The thickness of the intrinsic region is minimized to achieve a desired gamma discrimination factor of at least 1.0E+04. Material is removed from one of the p+ region or the n+ region and into the intrinsic layer to produce pillars with open space between each pillar. The open space is filed with a neutron sensitive material. An electrode is placed in contact with the pillars and another electrode is placed in contact with the side that is opposite of the intrinsic layer with respect to the first electrode.

Method for manufacturing solid-state thermal neutron detectors with simultaneous high thermal neutron detection efficiency (&#x3e;50%) and neutron to gamma discrimination (&#x3e;1.0E4)

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Fremont, CA, United States of America

Qinghui Shao