Integrated Device Technology, Inc.

Qinghua Yue

Pengfei Hu

Jinfu Chen

Lijie Zhao

Gao Song

A digital-to-analog converter (DAC) circuit includes a least significant bit (LSB) set of capacitors, each commonly coupled to an LSB node, and a most significant bit (MSB) set of capacitors, each coupled to an MSB node. A section-coupling capacitor couples the LSB and MSB nodes. The LSB node exhibits a parasitic capacitance, which tends to introduce a jump error voltage. Digital input signals are applied to the LSB and MSB capacitors, and in response, an analog output signal is developed on the MSB node. A compensation capacitor coupled to the MSB node has a compensation capacitance selected to offset the jump error voltage introduced by the parasitic capacitance. The compensation capacitor is enabled when all of the LSB capacitors are coupled to digital input signals having a logic '0' state. Otherwise, the compensation capacitor is disabled (e.g., left in a floating state).

Analog/digital or digital/analog conversion system having improved linearity

A digital-to-thermometer-code converter is disclosed for converting a digital signal into its thermometer-code equivalent. Embodiments of the digital-to-thermometer-code include a binary-to-control signal converter that generates a column control signal and a row control signal based on a binary input signal, and a control signal-to-thermometer-code decoder that includes an array of decoder circuit blocks coupled to receive the column control signal and the row control signal, wherein each of the decoder circuit blocks determine at least one bit of the thermometer-code output signal based on at least a first bit of the column control signal.

Thermo-decoder circuit

A digital-to-analog converter is disclosed for converting a digital signal into its analog equivalent. The digital-to-analog converter includes a two switches capable of coupling circuit nodes to ground, a scaling capacitor having a capacitance value that equals a unit capacitance value, a first array of capacitors coupled to the first circuit node and a first switching array which couples the first array of capacitors to either ground or a reference voltage depending on the digital values of the least significant bits of the digital word being converted, a second array of capacitors coupled to the second circuit node and a second switching array which couples the second array of capacitors to either ground or the reference voltage depending on the digital values of the most significant bits of the digital word being converted.

Growing community of inventors

Shanghai, China

Qinghua Yue