Capital Microelectronics Co., Ltd.

Qinghua Xue

Zixian Chen

Xian Yang

Xueping Zhou

A circuit and method of power on initialization for a configuration memory of an FPGA. The circuit includes: a decoding circuit, a driving circuit, and a configuration memory, where when 0 is written for the 1time, the decoding circuit turns on a word line corresponding to an address in the configuration memory, and the driving circuit writes content of the word line into 0; and when 0 is written for the itime, the decoding circuit turns on at least one word line corresponding to at least one address in the configuration memory, and the driving circuit writes content of each word line in the at least one word line into 0, the number of the at least one address being less than or equal to a sum of addresses that have completed writing of 0 for the previous (i&#x2212;1)time.

Circuit and method of power on initialization for configuration memory of FPGA

A hot-swap protection circuit includes: a hot-swap circuit, a hot-swap detection circuit, and an N-well generation circuit, where the hot-swap detection circuit is configured to detect whether hot-swap is performed on the hot-swap circuit, and feed back a detection result to the N-well generation circuit; and the N-well generation circuit is configured to receive the detection result fed back by the hot-swap detection circuit, and output a control signal according to the detection result, to protect the hot-swap circuit. The hot-swap detection circuit is used to detect whether hot-swap is performed on the hot-swap circuit, and the detection result is fed back to the N-well generation circuit, so that the N-well generation circuit outputs a control signal according to the detection result fed back by the hot-swap detection circuit, to protect the hot-swap circuit, thereby preventing the hot-swap of the hot-swap circuit from burning a host or a peripheral device.

Hot-swap protection circuit

The present invention relates to a chip power supply method and a chip, where configuration memory array provides configuration voltage to an NMOS transmission gate, and an LDO circuit supplies power to the chip. The method includes: determining that a working state of the chip switches from a first state to a second state, where the first state and the second state are separately an initial mode, a program mode or a user mode; and adjusting, according to the working state of the chip, a configuration bit to adjust an output voltage of the LDO circuit. The present invention reduces power dissipation of the chip during memory configuration, and improves working performance thereof during the user mode.

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Beijing, China

Qinghua Xue