Lattice Semiconductor Corporation

Qinghong Wu

Yinan Shen

Liren Liu

A technique for mapping a plurality of configurable logic blocks in a programmable logic device, such as a field-programmable gate array (FPGA). The method includes adaptively adjusting one or more customer-specified constraints and can be implemented, for example, using a simulated annealing algorithm. During the refinement of the placement (i.e., assignment) of logic blocks in an FPGA, one or more constraints are adjusted by either selecting a customer-specified constraint value or specifying a new constraint value derived based on the actual circuit performance. The method provides substantial savings of computer time compared to the prior art placement methods and improves circuit performance, e.g., by enabling higher circuit operation frequencies.

Adaptive adjustment of constraints during PLD placement processing

A method for placing configurable logic blocks (CLBs) in a PLD, such as an FPGA. In one embodiment, after packing gates/clusters into blocks and then assigning those blocks to CLBs to generate an initial placement, the packing and/or placement of CLBs is changed prior to performing CLB routing. For each node of the most critical of the K most critical paths in the initial placement, moving the node to a different CLB is considered in order to reduce the criticality of that path. A move is applied if certain acceptability conditions are met. After the most critical path is improved, the criticality of the K paths is updated, and the procedure is repeated for the new most critical of the K updated paths. The method, which can be automated to reduce human intervention in the design process, improves circuit performance, e.g., by enabling higher circuit operation frequencies.

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Santa Clara, CA, United States of America

Qinghong Wu