Huazhong University of Science and Technology

Zhejiang Lab

Qinggang Wang

Hai Jin

Xiaofei Liao

Long Zheng

Zhaozeng An

Ao Hu

The present invention relates to a hardware accelerator for hypergraph processing and its operating method, the hardware accelerator comprising: a data loader: for, in the presence of a data-centric load-trigger-reduce execution model, reading hypergraph partition data from an off-chip memory successively according to hypergraph data structure and an order of hypergraph partitions; an address translator, for deploying the hypergraph data into a private register of a processor and/or into a buffer memory according to a priority level of loaded data, and recording corresponding offset information; a task trigger, for generating computing tasks according to the loaded data, and scheduling the computing tasks into the processor; the processor, for receiving and executing the computing tasks; a reducer, for scheduling intermediate results into a first-priority-data reducer unit or a second-priority-data reducer unit depending on the priority level of the data so as to execute a reducing operation for the intermediate results. In view of the shortcomings of task-centric hardware accelerators, the present invention can prevent any possible data conflict during parallel execution of multiple processing units.

Hardware accelerator for hypergraph processing and operating method thereof

The present invention relates to a dynamic memory management apparatus and method for HLS, the apparatus has several searching and caching modules and several modifying and writing-back modules, the searching and caching modules are in connection with a DRAM storing module and a BRAM buffer, respectively, and the modifying and writing-back modules are in connection with the DRAM storing module and the BRAM buffer, respectively, the BRAM buffer is for caching information about nodes on a search path and registering information about modification made to the nodes. To remedy the defect that the traditional operating system is directly transplanted to the FPGA and has low execution efficiency, the present invention utilizes the advantage of the large capacity of the DRAM on the FPGA to realize efficient dynamic memory allocation and deallocation, and improve the usability and code reusability of HLS.

Dynamic memory management apparatus and method for HLS

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Wuhan, China

Qinggang Wang