Advanced Micro Devices Corporation

Advanced Micro Devices (shanghai) Co., Ltd.

Ati Technologies Ulc

Shanghai Biomodel Organism Science & Technology Co., Ltd.

Shanghai Research Center for Model Organisms

Qingcheng Wang

Jiasheng Chen

YunXiao Zou

Michael Mantor

Bin He

Angel E Socarras

Wei Yuan

Jun Li

Timour T Paltashev

Syed Zohaib M Gilani

Jian Fei

Ruling Shen

Zhugang Wang

A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.

Pipeline including separate hardware data paths for different instruction types

Systems, apparatuses, and methods implementing a hybrid matrix multiplication pipeline are disclosed. A hybrid matrix multiplication pipeline is able to execute a plurality of different types of instructions in a plurality of different formats by reusing execution circuitry in an efficient manner. For a first type of instruction for source operand elements of a first size, the pipeline uses N multipliers to perform N multiplication operations on N different sets of operands, where N is a positive integer greater than one. For a second type of instruction for source operand elements of a second size, the N multipliers work in combination to perform a single multiplication operation on a single set of operands, where the second size is greater than the first size. The pipeline also shifts element product results in an efficient manner when implementing a dot product operation.

Hybrid matrix multiplication pipeline

Described is a method and processing apparatus to improve power efficiency by gating redundant threads processing. In particular, the method for gating redundant threads in a graphics processor includes determining if data for a thread and data for at least another thread are within a predetermined similarity threshold, gating execution of the at least another thread if the data for the thread and the data for the at least another thread are within the predetermined similarity threshold, and using an output data from the thread as an output data for the at least another thread.

Method and processing apparatus for gating redundant threads

The invention discloses a kit which comprises a formulation containing artemisinin or the derivatives thereof, a formulation containing ribonuclease, and a specification.

Combined use of ribonuclease and artemisinin

Growing community of inventors

Shanghai, China

Qingcheng Wang