Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Nanjing Company, Limited

TSMC China Company Limited

Qingchao Meng

Lei Pan

Jing Ding

Huaixin Xian

Zhang-Ying Yan

Yi-Ting Chen

Yang Zhou

Yu-Ren Chen

Changlin Huang

Bright Li

Shao-Yu Chou

Shang-Chih Hsieh

Jerry Chang Jui Kao

Ying Fang Huang

Liu Han

Kai Zhou

J B Zhang

A circuit includes an input circuit, a level shifter circuit and an output circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second or a third input signal. The level shifter circuit is coupled to the input circuit and a second voltage supply, and configured to receive a first enable signal, the second or third input signal, and to generate a first signal responsive to the first enable signal, the second input signal or the third input signal. The level shifter circuit includes a header circuit coupled to a first node, and is configured to enable or disable the level shifter circuit responsive to the first enable signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and is configured to generate an output signal.

Level shifter circuit and method of operating the same

An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, a branch-two transistor, and a clock gating circuit. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is electrically connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is electrically connected to the first node. The clock gating circuit for generating a gated clock signal receives a latch output signal which is latched to a logic level of either a first node signal or a second node signal.

Method of and apparatus for controlling clock signal

A semiconductor device has a cell region including active regions that extend in a first direction and in which are formed components of transistors. The transistors of the cell region are arranged to function as a scan insertion D flip flop (SDFQ). The SDFQ includes a multiplexer serially connected at an internal node to a D flip-flop (FF). The transistors of the multiplexer include data transistors for selecting a data input signal, the data transistors having a first channel configuration with a first channel size, and scan transistors of the multiplexer for selecting a scan input signal, the scan transistors having a second channel configuration with a second channel size. The second channel size is smaller than the first channel size.

Multiplexer for SDFQ having differently-sized scan and data transistors, semiconductor device including same and methods of manufacturing same

An integrated circuit (IC) device includes first and second power rails extending in a first direction, a third power rail extending in the first direction between the first and second power rails, gate structures extending perpendicular to the first direction, each of two endmost gate structures extending continuously between endpoints underlying the first and second power rails, and first through fourth pluralities of active areas extending in the first direction between the endmost gate structures. Active areas of each of the first through fourth pluralities of active areas are aligned in the first direction, a first portion of the gate structures and first through fourth pluralities of active areas is configured as a functional circuit, and a second portion of the gate structures and first through fourth pluralities of active areas is configured as one of a decoupling capacitor or an antenna diode.

Combined function IC cell device, layout, and method

A method includes: forming first, second, and third NWs; forming form first to fourth transistors in corresponding first to fourth groups of active regions, connecting selected transistors amongst the first and second transistors to form first and second input circuits respectively receiving a first input signal in a first domain and a second input signal in the first domain; connecting selected transistors amongst the first and third transistors and amongst the first and fourth transistors to respectively form a first single bit level shifter (SBLS) and a second SBLS; each SBLS operates in the second domain and receives correspondingly versions of the first and second input signals; and connecting selected transistors amongst the first and third transistors to form a control circuit for toggling the first and second SBLSs between a normal and a standby state, a portion of the control circuit and the first SBLS sharing the second NW.

Method of method of forming a multi-bit level shifter

An integrated circuit includes a middle active-region structure between a group-one active-region structure and a group-two active-region structure. The integrated circuit also includes a main circuit, a group-one circuit, and a group-two circuit. The main circuit includes at least one boundary gate-conductor intersecting the middle active-region structure. The group-one circuit includes a group-one isolation structure separating the group-one active-region structure into a first part in the group-one circuit and a second part in a first adjacent circuit. The group-two circuit includes a group-two isolation structure separating the group-two active-region structure into a first part in the group-two circuit and a second part in a second adjacent circuit.

Circuit arrangements having reduced dependency on layout environment

An integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. The first time delay circuit has a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal. The second time delay circuit has a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal. The transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. The gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit.

Timing circuit arrangements for flip-flops

A multi-bit level-shifter (MBLS) includes two or more input circuits correspondingly configured to operate in a first voltage domain. The MBLS also includes two or more single bit level shifters (SBLSs) electrically coupled correspondingly to the two or more input circuits, and correspondingly configured to operate in a second voltage domain. The MBLS also includes a control circuit configured to toggle each of the two or more SBLSs between a normal mode and a standby mode according to a toggle-control signal received from the control circuit.

Multi-bit level shifter and method of operating same

A voltage level shift circuit comprises a first pair of transistors and a second pair of transistors. A first transistor of the second pair of transistors is coupled with an input signal terminal. A second transistor of the transistors of the second pair of transistors is coupled with an inverted input signal terminal. The transistors of the second pair of transistors are cross-coupled with the transistors of the first pair of transistors. The voltage level shift circuit also comprises a third pair of transistors. The transistors of the third pair of transistors are coupled with the transistors of the first pair of transistors and the transistors of the second pair of transistors. A first transistor of the third pair of transistors is directly coupled with an output signal terminal and second transistor of the third pair of transistors is directly coupled with an inverted output signal terminal.

Voltage level shift circuit for multiple voltage integrated circuits

A device includes a transistor cascode circuit including a first transistor configured to pull up voltage of a bulk and a node in response to a first control signal, and a second transistor configured to pull up voltage of an interface (I/O) pin in response to a second control signal. The device further includes a third transistor configured to pull down voltage of the I/O pin in response to a third control signal, and a feedback circuit configured to turn off the first transistor when the voltage of the I/O pin is above a predetermined level during a failsafe period.

Failsafe interface circuit and related method

A device includes a first level shifter, a switch, and a control circuit. The first level shifter is electrically connected to a pad. The switch has an input terminal electrically connected to an input terminal of the first level shifter, and an output terminal electrically connected to an output terminal of the first level shifter. The control circuit is electrically connected to a control terminal of the switch.

Multiple voltage input buffer and related method

Some embodiments relate to an IC that includes an ESD-susceptible circuit. The IC includes a number of IC pads that are electrically coupled to respective nodes on the ESD-susceptible circuit. The IC pads are electrically accessible from external to the IC, and include one or more power supply pads and one or more I/O pads. The IC also includes a number of ESD protection devices coupled to the plurality of IC pads, respectively. A trigger circuit on the IC is configured to detect an ESD event impingent on a power supply pad and, in response to the detection, to trigger concurrent shunting of energy of the ESD event over both an ESD clamp element of an I/O pad and an ESD clamp element of the power supply pad. Other embodiments are also disclosed.

ESD protection scheme using I/O pads

An over-driver, voltage level shift circuit for use with multiple voltage integrated circuits. The voltage level shift circuit includes a first pair of PMOS transistors, a second pair PMOS transistors and a third pair of PMOS transistors using a high supply voltage source VDDH and a low supply voltage source to voltage level shift input signals having a first voltage operating range to an output signal having a second voltage operating range higher then the first voltage operating range. Some embodiments include a fourth set of transistors and a fifth set of transistors to receive a medium supply voltage source VDDM between the high supply voltage source VDDH and a low supply voltage source and another set of input signals operating a voltage operating range different than the first operating range. The voltage level shift circuit selectably switches between a plurality of different voltage operating ranges for the second voltage operating range.

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Shanghai, China

Qingchao Meng