Western Digital Technologies, Inc.

Hgst Netherlands, B.v.

International Business Machines Corporation

Sandisk Technologies Inc.

Qingbo Wang

Zvonimir Z Bandic

Cyril Guyot

Dejan Vucinic

Robert Eugeniu Mateescu

Luiz M Franca-Neto

Frank R Chu

Hessam Mahdavifar

Haiwen Xi

Neil Leslie Robertson

Jordan Asher Katine

Yang Li

Patrick Braganca

Meng Ye

Long Cheng

Dong Jun Lan

Liang Liu

Hao Wang

Li Li

Ronald Patrick Doyle

Martin Lueker-Boden

Chao Sun

Timothy Tsai

Rui Xiong Tian

Sheng Lu

Xing X Fang

Ruth Edith Willenborg

Ken Qing Yang

Dongyang Li

Stephen J Schmidt

Ying Li

Yang Zhao

Ashwin Narasimha

Anand Kulkarni

Minghai Qin

Luis Vitorio Cargnini

Xing Jin

Le He

Zhi Le Zou

Damien Cyril Daniel Le Moal

Filip Blagojevic

Jaco Hofmann

Gang Crl Wang

Mitchell Robert Fream

Adarsha Balaji

A mesh network-on-a-chip (NOC) with heterogenous routers for use with homogenous processing elements. Some of the routers are configured differently from other routers to interface more efficiently with particular physical resources that the processing elements require, such as particular input/output or memory devices. For example, one router is configured for use with the Peripheral Component Interconnect Express (PCIe) protocol, whereas another router is configured for use with the InterLaken communication protocol. Still further, the overall system is configured so that the various physical resources are physically adjacent to the particular router that is designed to access the resource to help ensure fair access by each processing element of the NOC to the particular resources that are required. The NOC may be part of a large manycore system on field programmable gate array (FPGA). The methods and apparatus described herein are generally applicable to all system-on-a-chip (SOC) designs.

Mesh network-on-a-chip (NOC) with heterogeneous routers

A memory device includes a first memory and a second memory that caches data stored in the first memory. At least one controller of the memory device receives page fault information from a host. The page fault information results from a request for data by the host that is stored in the first memory but is not cached in the second memory when requested by the host. The memory device uses the received page fault information for one or more inputs into a prefetch model trained by Machine Learning (ML) to generate at least one inference. Based at least in part on the at least one inference, prefetch data is cached in the second memory. In one aspect, the page fault information is used to train the prefetch model. In another aspect, the page fault information includes at least one virtual address used by the host for the requested data.

Memory prefetch based on machine learning

A network device includes at least one control path port and data path ports configured to communicate on a network. A connection request is received from a host via a control path port, and a resource of the network device is allocated to the host. A data path port is determined from among the plurality of data path ports for communication between the host and the allocated resource. An indication of the determined data path port is sent to the host via the control path port for communication on a data path between the host and the allocated resource. In one aspect, a network interface includes at least one control path port and a first plurality of data path ports configured to communicate on a network. A connection request is received from a host via a control path port, and a locally connected device is allocated to the host.

Disaggregation of control path and data path

A Virtual Machine (VM) is created utilizing a virtual Operating System (OS) disk and virtual application disks, each of which may be from disparate third party suppliers. One or more files in the virtual application disk are then linked to a specific file system location (node) in the virtual OS disk.

Creating a virtual machine containing third party code

A method and a storage system are provided for implementing enhanced solid state storage class memory (eSCM) including a direct attached dual in line memory (DIMM) card containing Dynamic Random Access Memory (DRAM), and at least one 5 non-volatile memory, for example, Phase Change Memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque RAM (STT-RAM), and NAND Flash chips. An eSCM processor controls selectively allocating data among the DRAM, and the at least one non-volatile memory primarily based upon a data set size.

Apparatus and method for low power low latency high capacity storage class memory

Systems and methods are disclosed for determining whether data to be written to a memory should be deduplicated. In some implementations, a method is provided. The method includes determining whether data to be written to a memory should be deduplicated based, at least in part, on status information of a controller and media characteristics of the memory, wherein the status information of the controller indicates a level of resources available for a deduplication operation. In response to determining that the data should be deduplicated, determining whether the data is duplicative based on the type of memory the data is being written to.

Selective deduplication based on data storage device controller status and media characteristics

A system according to one embodiment includes a pinned layer; a spacer layer above the pinned layer; a free layer above the spacer layer; a heating device, for heating the free layer to induce a paramagnetic thermal instability in the free layer whereby a magnetization of the free layer randomly switches between different detectable magnetic states upon heating thereof; and a magnetoresistance detection circuit for detecting an instantaneous magnetic state of the free layer.

Random number generator by superparamagnetism

Techniques for providing file system functionality over a PCIe interface are disclosed. In some embodiments, the techniques may be realized as a method for providing file system functionality over a PCIe interface including receiving from a host device a storage command, specially devised for such a standard protocol, at a PCIe-based device controller, parsing, using at least one computer processor of the PCIe-based device controller, the storage command, traversing, using PCIe-based device controller, one or more portions of file system metadata of an associated storage media device, wherein the PCIe-based device controller is configured to traverse the one or more portions of file system metadata based on the parsed storage command independent of any subsequent communication with the host device, and returning data to the host device.

System and method to provide file system functionality over a PCIe interface

A system includes a bus, at least one processor coupled to the bus, and a storage device coupled to the bus. The storage device includes storage class memory, a buffer; and a controller. The controller is configured to receive an instruction to provide data to the bus. Responsive to receiving the instruction to provide data to the bus, the controller is configured to retrieve data from the storage class memory, update the buffer to represent the data retrieved from the storage class memory, and output, at the bus, an indication that data responsive to the instruction to provide data to the bus is available at the buffer. The at least one processor is configured to refrain from modifying local data corresponding to the instruction to provide data to the bus after the controller receives the instruction to provide data to the bus and before the controller outputs the indication.

Coherent controller

An approach for fingerprinting large data objects at the wire speed has been disclosed. The techniques include Fresh/Shift pipelining, split Fresh, optimization, online channel sampling, and pipelined selection. The architecture can also be replicated to work in parallel for higher system throughput. Fingerprinting may provide an efficient mechanism for identifying duplication in a data stream, and deduplication based on the identified fingerprints may provide reduced storage costs, reduced network bandwidth consumption, reduced processing time and other benefits. In some embodiments, fingerprinting may be used to ensure or verify data integrity and may facilitate detection of corruption or tampering. An efficient manner of generating fingerprints (either via hardware, software, or a combination) may reduce a computation load and/or time required to generate fingerprints.

Hardware efficient rabin fingerprints

Hardware efficient fingerprinting

The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.

Doorless protocol having multiple queue read requests in flight

Doorbell-less protocol for solid state drive interface

In one embodiment, a method for deploying a data processing system in a virtual environment includes deploying a data processing system call interface in a virtual machine in a virtualization environment, the system call interface being configured to trigger a locally called data processing instruction. The method also includes deploying a data processing driver in a virtual machine management platform in the virtualization environment, the data processing driver being configured to read the data processing instruction triggered by the system call interface. Moreover, the method includes deploying a data processing instruction optimizer in the virtualization environment, the optimizer being configured to optimize the data processing instruction read by the deployed data processing driver.

System, method and computer program product for data processing and system deployment in a virtual environment

Growing community of inventors

Irvine, CA, United States of America

Qingbo Wang