The 13th Research Institute of China Electronics Technology Group Corporation

The 13ᵗʰ Research Institute Of China Electronics Technology Group Corporation

The 13th Research Institute of China Electronics Technology

Qingbin Liu

Zhihong Feng

Zezhao He

Jingjing Wang

Chuangjie Zhou

Cui Yu

Jia Li

Xuedong Gao

Cui Wei

Jianchao Guo

Disclosed are a preparation method for a diamond-based field effect transistor and a field effect transistor, relating to the technical field of semi-conductors. Said method comprising: forming a conductive layer on the upper surface of a diamond layer; the diamond layer being a high-resistance layer; manufacturing an active region mesa on the diamond layer; manufacturing, on the conductive layer, a source electrode on a first region corresponding to a source electrode region, and manufacturing, on the conductive layer, a drain electrode on a second region corresponding to a drain electrode region; depositing, on the conductive layer, a photocatalyst dielectric layer on the upper surface of a third region corresponding to a source and gate region, and depositing, on the conductive layer, the photocatalyst dielectric layer on the upper surface of a fourth region corresponding to a gate and drain region; illuminating the photocatalyst dielectric layer; depositing, on the conductive layer, a gate dielectric layer on a fifth region corresponding to gate electrode region, manufacturing a gate electrode on the upper surface of the gate dielectric layer. The present invention can reduce the on-resistance of devices.

Method for preparing diamond-based field effect transistor, and corresponding field effect transistor

The present application discloses a semiconductor device and a method for forming a p-type conductive channel in a diamond using an abrupt heterojunction, which pertain to the technical field of fabrication of semiconductor devices. The method includes: forming a diamond layer on a substrate; forming one or multiple layers of a heterogeneous elementary substance or compound having an acceptor characteristic on an upper surface of the diamond layer; forming a heterojunction at an interface between the diamond layer and an acceptor layer; forming two-dimensional hole gas at one side of the diamond layer with a distance of 10 nm-20 nm away from the heterojunction; and using the two-dimensional hole gas as a p-type conductive channel. The method enables a concentration and a mobility of carriers to maintain stable at a temperature range of 0&#xb0; C.-1000&#xb0; C., thereby realizing normal operation of the diamond device at high temperature environment.

Semiconductor device and method for forming p-type conductive channel in diamond using abrupt heterojunction

The present application discloses a semiconductor device and a method for forming an n-type conductive channel in a diamond using a heterojunction, which pertain to the technical field of fabrication of semiconductor devices. The method comprises: forming a diamond layer on a substrate; and depositing a ternary compound having a donor characteristic and graded components on an upper surface of the diamond layer to form a first donor layer, forming a graded heterojunction at an interface between the diamond layer and the first donor layer, forming two-dimensional electron gas at one side of the diamond layer adjacent to the graded heterojunction, and using the two-dimensional electron gas as the n-type conductive channel. The method enables a concentration and a mobility of carriers in the n-type diamond channel to reach 1013 cmand 2000 cm/V&#xb7;s respectively.

Semiconductor device and method for forming n-type conductive channel in diamond using heterojunction

A method for manufacturing a graphene transistor based on self-aligning technology, the method comprising: on a substrate (), forming sequentially graphene material (), a metal film (), and photoresist patterns () formed by lithography, removing the metal film and the graphene material uncovered by the photoresist, forming an active area, and metal electrodes () of a source, a gate, and a drain of the transistor, wherein the source electrodeand drain electrodeare connected with a metal of the active region, and forming gate photoresist patterns () between the source and the drain by lithography, etching off the exposed metal, forming sequentially a seed layer (), a gate dielectric layer (), and gate metal () on the exposed graphene surface, and finally forming a graphene transistor.

Method for manufacturing graphene transistor based on self-aligning technology

Growing community of inventors

Shijiazhuang, China

Qingbin Liu