United States of America As Represented by the Secretary of the Air Force

Qing Wu

Richard W Linderman

Yiran Chen

Mark Herron Linderman

Hai Li

Garrett Rose

Dennis Fitzgerald

Miao Hu

Robinson E Pino

Mark D Barnell

Oinru Qiu

An apparatus for a microprocessor computer system and method for configuring the same where said microprocessor computer system comprises a processor core and at least one hardware buffer FIFO with memory-mapped head and tail that handles data movement among the processor cores, networks, raw data input and outputs, and memory. The method for configuring said microprocessor computer system comprises utilizing a FIFO auxiliary processor to process said data traversing said hardware FIFO; utilizing said hardware FIFOs to efficiently pipe data through functional blocks; and utilizing a FIFO controller to perform DMA operations that include non-unit-stride access patterns and transfers among processor cores, networks, raw data input and outputs, memory, and other memory-mapped hardware FIFOs.

Systems and methods for mapping hardware FIFO to processor address space

Systems and method for mapping FIFOs to processor address space

Method and apparatus for performing close-loop programming of resistive memory devices in crossbar array based hardware circuits and systems. Invention provides iterative training of memristor crossbar arrays for neural networks by applying voltages corresponding to selected training patterns. Error is detected and measured as a function of the actual response to the training patterns versus the expected response to the training pattern.

Method and apparatus for performing close-loop programming of resistive memory devices in crossbar array based hardware circuits and systems

Invention provides an apparatus and method for performing signal processing on a crossbar array of resistive memory devices. The invention is implemented using one or multiple crossbar arrays of resistive memory devices in conjunction with devices for converting input real number representations to voltage waveforms, devices for converting current waveforms into voltage waveforms, and devices for converting voltage waveforms to real numbers outputs.

Method and apparatus for performing signal processing on a crossbar array of resistive memory devices

An apparatus that performs the mathematical matrix-vector multiplication approximation operations using crossbar arrays of resistive memory devices (e.g. memristor, resistive random-access memory, spintronics, etc.). A crossbar array formed by resistive memory devices serves as a memory array that stores the coefficients of a matrix. Combined with input and output analog circuits, the crossbar array system realizes the method of performing matrix-vector multiplication approximation operations with significant performance, area and energy advantages over existing methods and designs. This invention also includes an extended method that realizes the auto-associative neural network recall function using the resistive memory crossbar architecture.

Apparatus for performing matrix vector multiplication approximation using crossbar arrays of resistive memory devices

A method for context-aware text recognition employing two neuromorphic computing models, auto-associative neural network and cogent confabulation. The neural network model performs the character recognition from input image and produces one or more candidates for each character in the text image input. The confabulation models perform the context-aware text extraction and completion, based on the character recognition outputs and the word and sentence knowledge bases.

Method for context aware text recognition

CMOS-memristor circuit is constructed to behave as a trainable artificial synapse for neuromorphic hardware systems. The invention relies on the memristance of a memristor at the input side of the device to act as a reconfigurable weight that is adjusted to realize a desired function. The invention relies on charge sharing at the output to enable the summation of signals from multiple synapses at the input node of a neuron circuit, implemented using a CMOS amplifier circuit. The combination of several memristive synapses and a neuron circuit constitute a neuromorphic circuit capable of learning and implementing a multitude of possible functionalities.

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Manlius, NY, United States of America

Qing Wu