Omnivision Technologies, Inc.

Qing Qin

Hoon Ryu

Tiejun Dai

Zhe Gao

Ling Fu

Taehyung Jung

Zhiyong Zhan

Chia Ming Chen

A pixel circuit includes a photodiode configured to photo generate image charge in response to incident light, a floating diffusion coupled to receive the image charge from the photodiode, a transfer transistor coupled between the photodiode and the floating diffusion to transfer the image charge from the photodiode to the floating diffusion, a reset transistor coupled between a variable voltage source and the floating diffusion, wherein the reset transistor is configured to be switched in response to a reset control signal, and a lateral overflow integration capacitor (LOFIC) coupled between the variable voltage source and the floating diffusion. The variable voltage source is configured to output a high-voltage level during a high conversion gain (HCG) reset signal readout and an HCG image signal readout, and a mid-voltage level during a LOFIC image signal readout and a LOFIC reset signal readout.

CAPMID design in VRFD for HDR structure

A novel bit storage circuit includes a first voltage supply line, a second voltage supply line, a bit line, a latch, a first switching transistor, and a blocking transistor. The latch includes an input and an output. The first switching transistor includes a first terminal, a second terminal, and a control terminal. The first switching transistor is operative to provide a conductive path and a non-conductive path between the bit line and the input of the latch responsive to a first control signal being asserted on the control terminal of the first switching transistor. The blocking transistor includes a control terminal and is operative to selectively provide a conductive path and a non-conductive path between the input of the latch and the second voltage supply line responsive to a second control signal. The blocking transistor facilitates the use of a single bit line.

Single bitline SRAM pixel and method for driving the same

An event driven sensor includes an arrangement of photodiodes including an inner portion laterally surrounded by an outer portion. An outer pixel cell circuit is coupled to generate an outer pixel value in response to photocurrent generated by the outer portion. The outer pixel value is a binned signal representative of an average value of brightness of incident light on the arrangement of photodiodes. An inner pixel cell circuit is coupled to the inner portion to generate an inner pixel value in response to photocurrent generated by from the inner portion. An event driven circuit is coupled to the outer pixel cell circuit and the inner pixel cell circuit. The event driven circuit is coupled to generate an output signal responsive to an inner brightness indicated by the inner pixel value relative to an outer brightness indicated by the outer pixel value.

Event driven pixel for spatial information extraction

An image sensor has an array of pixels configured in multiple blocks; each block coupled to a separate analog-to-digital converter (ADC) to provide digitized image data. The ADCs feed digitized images into an image RAM; and the image RAM feeds digitized images to an alignment buffer in a first pixel order. The alignment buffer provides digitized images to an image processor in a second pixel order different from the first pixel order. In an embodiment, the alignment buffer uses a multiport RAM. In another embodiment, the alignment buffer uses first and second alignment buffer RAMs, writing one alignment buffer RAM while reading the other alignment buffer RAM to provide image data to the image processor. In embodiments, the alignment buffer provides digitized images in an order selectable between a full resolution and a reduced resolution order, and selectable between a right-to-left and left-to-right order.

Configurable interface alignment buffer between DRAM and logic unit for multiple-wafer image sensors

A bond-per-pixel-block image sensor has a pixel array including multiple pixel blocks with selection circuitry to couple signals to an ADC. The image sensor has an image RAM of DRAM superblocks, each superblock with multiple DRAM blocks each having tristate output driving an image RAM output bus, and data input from several of the ADCs. Each DRAM block has an address multiplexor coupled to read and write addresses. DRAM blocks of each superblock are written simultaneously with data wider than a width of the image RAM output bus. A method of capturing and processing images includes reading a first image frame from pixels of a pixel block through ADCs; writing digital pixel data for the first image frame in a first DRAM superblock; and reading pixel data into an alignment buffer. The method includes overlapping reading the first image frame with writing a second image frame into a second superblock.

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Santa Clara, CA, United States of America

Qing Qin