Stmicroelectronics Gmbh

International Business Machines Corporation

Globalfoundries Inc.

Avago Technologies International Sales Pte. Limited

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Stmicroelectronics (crolles 2) Sas

Avago Technologies General IP (singapore) Pte. Ltd.

Commissariat À L'énergie Atomique Et Aux Énergies Alternatives

Bell Semiconductor, LLC

Broadcom Corporation

Stmicroelectronics S.a.

Qing Liu

Ruilong Xie

Chun-chen Yeh

Nicolas J Loubet

Xiuyu Cai

Prasanna Khare

Bruce Bennett Doris

John H Zhang

Kangguo Cheng

Shom Ponoth

Maud Vinet

Kejia Wang

Ali Khakifirooz

Akira Ito

Laurent Grenouillet

Yannick Le Tiec

Stephane Allegret-Maret

Pierre Morin

Thomas Skotnicki

Hong He

Andrew Mark Greene

Scott D Luning

Tenko Yamashita

Veeraraghavan S Basker

Junli Wang

Hemanth Jagannathan

Balasubramanian Pranatharthiharan

Daniel Chanemougame

Gauri V Karve

Chun-Chen Yeh

William James Taylor, Jr

Lisa F Edge

Walter Kleemeier

Salih Muhsin Celik

Hyun-Jin Cho

Claire Fenouillet-Beranger

Emmanuel Richard

Pierre Perreau

A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FIN FET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods

A fin-based field effect transistor (finFET) device may include a fin structure having a first portion, a second portion and a third portion. The finFET device may include a first gate structure disposed over at least part of the first portion, a first source/drain region disposed in the first portion, and a second drain/source region disposed in the third portion. Each of the first, second and third portions may include one or more fin portions. The total fin count in the second portion is fewer than the total fin count in the first portion. The second portion may include a drift region. Methods of fabricating a finFET are also disclosed. The finFET device provides a lower on-resistance and a higher breakdown voltage than conventional finFETs.

Fin-based field effect transistor (finFET) device with enhanced on-resistance and breakdown voltage

A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.

Method to co-integrate SiGe and Si channels for finFET devices

A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

Vertical tunneling FinFET

A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.

Forming replacement low-k spacer in tight pitch fin field effect transistors

A semiconductor structure includes a substrate having a top surface, pillar structures formed on top of the substrate, a gate conductor, a drain/source region and a source/drain region. Each pillar structure of the pillar structures includes a first end and a second end, and the first end is closer to the substrate than the second end. The gate conductor surrounds each of the pillar structures disposed between the first end and the second end. The drain/source region is at the top surface of the substrate and in contact with the first end of a first pillar structure of the pillar structures, and the source/drain region is at the top surface of the substrate and in contact with the first end of a second pillar structure of the pillar structures.

Folded channel vertical transistor and method of fabricating same

A fin-shaped field-effect transistor (finFET) device is provided. The finFET device includes a substrate material with a first surface and a bottom surface. The finFET device also includes a well region formed in the substrate material. The well region may include a first type of dopant. The finFET device also includes a fin structure disposed on the first surface of the substrate material. A portion of the fin structure may include the first type of dopant. The finFET device also includes an oxide material disposed on the first surface of the substrate material and adjacent to the portion of the fin structure. The finFET device also includes a first epitaxial material disposed over a portion of the fin structure. The first epitaxial material may include a second type of dopant.

Lateral double-diffused metal-oxide-semiconductor (LDMOS) fin field effect transistor with enhanced capabilities

A transistor device includes a substrate a first transistor structure. The first transistor structure includes a first fin structure on the substrate. The first fin structure includes a first doped region, and a second fin structure on the substrate spaced apart from the first fin structure. The second fin structure includes a second doped region and a third doped region spaced apart from the second doped region. The transistor device includes a first electrode on the second fin structure and covering a first end of the second fin structure.

Bi-directional transistor devices having electrode covering sidewall of the Fin structure

A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).

Integrated tensile strained silicon NFET and compressive strained silicon-germanium PFET implemented in FinFET technology

A transistor structure includes a substrate and a fin structure on the substrate. The fin structure includes an undoped portion, a first doped portion, and a second doped portion. The transistor structure includes an electrode on the fin structure between the first doped portion and the second doped portion, and an insulating layer on the fin structure. The transistor structure includes a first trench in the insulating layer at a first side of the fin structure and between the electrode and the second doped portion, and a second trench in the insulating layer at a second side of the fin structure and between the electrode and the second doped portion. The first trench includes a first conductive material, and the second trench includes a second conductive material.

Transistor structures

An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

Device having overlapping semiconductor fins oriented in different directions

A capacitor includes a shallow trench isolation (STI) layer disposed on top of a substrate. The capacitor also includes a first dielectric layer disposed on top of the STI layer. The capacitor further includes a metallization diffusion (MD) layer disposed within both of the STI layer and the first dielectric layer.

Ultra high density metal-oxide-metal capacitor

A dual width SOI FinFET is disclosed in which different portions of a strained fin have different widths. A method of fabrication of such a dual width FinFET entails laterally recessing the strained fin in the source and drain regions using a wet chemical etching process so as to maintain a high degree of strain in the fin while trimming the widths of fin portions in the source and drain regions to less than 5 nm. The resulting FinFET features a wide portion of the fin in the channel region underneath the gate, and a narrower portion of the fin in the source and drain regions. An advantage of the narrower fin is that it can be more easily doped during the growth of the epitaxial raised source and drain regions.

Dual width FinFET

Growing community of inventors

Watervliet, NY, United States of America

Qing Liu