Agilent Technologies, Inc.

Skyworks Solutions, Inc.

Silicon Laboratories Inc.

Qing Gan

Frank Sigming Geefay

Anthony James Lobianco

Richard C Ruby

Robert W Warren

Domingo A Figueredo

Andrew Thomas Barfknecht

Cheol Hyun Han

Steve Xin Liang

Ann Mattos

Emmanuel Philippe Quevy

Allen Chien

An encapsulated MEMS device and a method to form an encapsulated MEMS device are described. An apparatus includes a first substrate having a silicon-germanium seal ring disposed thereon and a second substrate having a metal seal ring disposed thereon. The metal seal ring is aligned with and bonded to the silicon-germanium seal ring to provide a sealed cavity. A MEMS device is housed in the sealed cavity. A method includes forming a silicon-germanium seal ring on a first substrate and forming a metal seal ring on a second substrate. The metal seal ring is bonded to the silicon-germanium seal ring to provide a sealed cavity that houses a MEMS device.

Encapsulated MEMS device and method to form the same

A through via is constructed in a two-stage process. A void in a portion of the depth of the substrate is filled from a first surface of the semiconductor substrate creating an enclosed volume within the substrate. Thereafter, the enclosed volume is exposed and the remaining portion of the void is filled.

Methods for forming a through via

According to an exemplary embodiment, a wafer level package includes a device wafer including at least one device wafer contact pad and a device, and where the at least one device wafer contact pad is electrically connected to the device. The wafer level package includes a first polymer layer situated over the device wafer. The wafer level package includes at least one passive component situated over the first polymer layer and having a first terminal and a second terminal. The first terminal of the at least one passive component is electrically connected to the at least one device wafer contact pad. The wafer level package includes a second polymer layer situated over the at least one passive component. The wafer level package includes at least one polymer layer contact pad situated over the second polymer layer and electrically connected to the second terminal of the at least one passive component.

Method for fabricating a wafer level package with device wafer and passive component integration

Wafer level package including a device wafer integrated with a passive component

A gasket encloses a hermetically sealed environment between a cap wafer and a base wafer. The gasket is bonded to the base wafer using bonding material. The bonding material can be one or more of many substances that exhibit acceptable adhesion, sealing, and other properties that ensure a hermetically sealed environment. The gasket is carved out from the cap wafer material itself. The cap wafer is typically made of extremely strong and rigid material such as silicon. Since the gasket is made from the cap wafer, the gasket itself is also extremely strong and rigid.

Wafer-level package with silicon gasket

A sloped via contact is used to connect a contact on the front side of a wafer to a contact on the back side of the wafer. The walls of a small (less than 50-80 microns wide) via have typically been difficult to coat with metal. The present invention forms a small via with sloped walls, allowing easy access to the inside walls of the via for metal sputtering or plating. The small via can be formed using a dry etch process such as the well-known deep reactive ion etching (DRIE) process. Using any isotropic plasma etch process, the walls of the via are further etched from the wafer backside to create sloped walls in the via. The via is then coated with metal to make it conductive.

Sloped via contacts

A method for separating dies on a wafer includes etching channels around the dies on a first side of the wafer, mounting the first side of the wafer to a quartz plate with an UV adhesive, and grinding a second side of the wafer until the channels are exposed on the second side of the wafer. At this point, the dies are separated but held together by the UV adhesive on the quartz plate. The method further includes mounting a second side of the wafer to a tack tape, exposing UV radiation through the quartz plate to the UV adhesive. At this point, the UV adhesive looses its adhesion so the dies are held together by the tack tape. The method further includes dismounting the quartz plate from the first side of the wafer and picking up the individual dies from the tack tape.

Die singulation using deep silicon etching

A method for forming a wafer package includes forming a die structure, wherein the die structure includes a first wafer, a device mounted on the first wafer, a second wafer mounted atop the first wafer with a first seal ring around the device and a second seal ring around a via contact. The method further includes forming a trench in the second wafer around the first seal ring, filling the trench and the via contact with a sealing agent, patterning a topside of the second wafer to removed the excessive sealing agent and to expose a contact pad of the via contact, and singulating a die around the first seal ring.

Film deposition to enhance sealing yield of microcap wafer-level package with vias

A method and apparatus for determining the hermeticity of a semiconductor package is disclosed. Gas is introduced into the semiconductor package during packaging. Vacuum suction is then applied to the package. If the package has any leaks, the gas within will escape. The package is next scanned using a spectrometer. If the spectrometer does not detect any gas within the package cavity, the package is not hermetically sealed. In an alternate embodiment, the device is packaged first, and then immersed in a pressurized liquid. If the package has a leak, the pressure on the liquid will force liquid into the package cavity. The cavity of a properly sealed package will remain empty and dry. The package is scanned using a spectrometer. If the spectrometer detects liquid within the package, the package is not hermetically sealed.

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Fremont, CA, United States of America

Qing Gan