Intel Corporation

Qing A Zhou

Daoqiang Lu

Wei Shi

Jiangqi He

Xiang Yin Zeng

Yiqun Bai

Jianqqi He

Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die on the other substrate. Other embodiments are described and claimed.

Multi-chip assembly with optically coupled die

In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed.

Forming compliant contact pads for semiconductor packages

Some embodiments of the present invention include apparatuses and methods relating to integrated micro-channels for removing heat from 3D through silicon architectures.

Integrated micro-channels for 3D through silicon architectures

A separable electrical connection may be provided with a landside pad on one of two electrical components to be joined. The landside pad may be made up of two parts, including a flat portion and a raised edge formed on the flat portion. In some embodiments, the raised edge may have a closed geometric shape. Then, a socket contact engaging the junction between the flat portion and the raised edge is prevented from sliding off of the landside pad by the raised edge. In addition, dual areas of electrical connection can be established between both the flat portion and raised edge of the landside pad and the correspondingly shaped pair of portions on the socket. This increases the electrical efficiency of the connection and its security.

Substrate with raised edge pads

An integrated circuit ('IC') package having two or more dice stacked on a substrate and electrically coupled using two or more different connection technologies may improve high-speed input/output ('I/O') bandwidth. In an embodiment, one die is a processor and at least one other die is a dynamic random access memory (&#x201c;DRAM&#x201d;). One or more of the dice may be thinned and placed between the substrate and a portion of one or more of the other dice, which may be horizontally offset. One or more of the dice may be embedded in the substrate. The dice may be coupled to each other and to the substrate using a combination of controlled-collapse chip connection (&#x201c;C4&#x201d;) and wirebonding connection technologies. Methods of fabrication, and application of the package to an electronic assembly and to an electronic system, are also described.

Electronic assembly with stacked IC's using two or more different connection technologies and methods of manufacture

A system may include a microprocessor die, an integrated circuit package substrate, and a die disposed between the microprocessor die and the integrated circuit package substrate. In some embodiments, the integrated circuit package substrate defines a first cavity, and the die is disposed at least partially within the first cavity.

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Chandler, AZ, United States of America

Qing A Zhou