Sk Hynix Nand Product Solutions Corp.

Intel Corporation

Qihua Dai

Sanjeev N Trika

Ziye Yang

Gang Cao

Piotr Wysocki

Xiaodong Liu

Changpeng Liu

James R Harris

Jonathan M Hughes

Benjamin Walker

Jackson Ellis

Gregory Tucker

Vinodh Gopal

Weigang Li

Systems and methods for a controller including controller memory and logic are presented herein. The logic is configured to control access to a persistent storage media and, in response to one or more commands, determine an intermediate parity value based on a first parity calculation by sending a uni-directional command to the persistent storage media. The logic is further configured to store, in the controller memory, the intermediate parity value, and determine a final parity value based on the intermediate parity value and a second parity calculation.

ON-SSD erasure coding with uni-directional commands

Systems and methods for a controller including controller memory and logic are presented herein. The logic is configured to control access to a persistent storage media and, in response to one or more commands, the logic determines an intermediate parity value based on a first parity calculation, and using the intermediate parity value determines a final parity value based on the intermediate parity value and a second parity calculation. Determining the intermediate parity value includes sending a uni-directional command to read an old data value from an address indicated in the uni-directional command, perform an exclusive-or operation on the old data value and a new data value indicated in the uni-directional command to determine the intermediate parity value and store, in the persistent storage media, the intermediate parity value at a location associated to an index indicated in the uni-directional command.

On-SSD erasure coding with uni-directional commands

Technologies for adaptive processing of multiple buffers is disclosed. A compute device may establish a buffer queue to which applications can submit buffers to be processed, such as by hashing the submitted buffers. The compute device monitors the buffer queue and determines an efficient way of processing the buffer queue based on the number of buffers present. The compute device may process the buffers serially with a single processor core of the compute device or may process the buffers in parallel with single-instruction, multiple data (SIMD) instructions. The compute device may determine which method to use based on a comparison of the throughput of serially processing the buffers as compared to parallel processing the buffers, which may depend on the number of buffers in the buffer queue.

Technologies for adaptive processing of multiple buffers

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Shanghai, China

Qihua Dai