Cirrus Logic Inc.

Silicon Laboratories Inc.

Panasonic Corporation

Qicheng Yu

Jerome E Johnston

Saroj Rout

Akhil K Garlapati

Axel Thomsen

Jerrell P Hein

Douglas F Pastorello

Bruce Philip Del Signore

Srisai Rao Seethamraju

Saibun Wong

Kenneth Kin Wai Wong

A sense channel signal processing block is time-domain multiplexed among multiple MEMS devices and utilizes an anti-aliasing filter disposed after track-and-hold switches, to prevent the bandwidth of the sense channel from being limited by the anti-aliasing filter. A multiplexed signal processor architecture performs dynamic calibration of all sensor error signals in response to environmental changes.

Method for calibration of a system with time-multiplexed sensors

A sense channel signal processing block is time-domain multiplexed among multiple MEMS devices and utilizes an anti-aliasing filter disposed after track-and-hold switches, to prevent the bandwidth of the sense channel from being limited by the anti-aliasing filter.

Time-domain multiplexed signal processing block and method for use with multiple MEMS devices

A technique that is readily implemented in monolithic integrated circuits includes a method including generating an output clock signal during a presence of a reference clock signal based, at least in part, on a digital control value indicating a phase difference between a feedback signal of a PLL and a reference clock signal. The method includes generating the output clock signal during an absence of the reference clock signal and based, at least in part, on an average digital control word indicating an average value of a number of samples of the digital control value during the presence of the reference clock signal, the number of samples preceding the absence of the reference clock signal by a delay period. The number of samples is selected from a plurality of numbers of samples and the delay period is selected from a plurality of delay periods.

Digital hold in a phase-locked loop

A first current source supplies a first charge amount responsive to a first pulse signal from the phase frequency detector and a second current source supplies a second charge amount according to a fixed value and a variable value. The variable value corresponds to a phase difference between a first feedback clock signal and a hypothesized feedback clock signal with reduced quantization noise. The first and second charge amounts are of opposite polarity. A single set of first and second current sources perform the functions of charge pump and noise reduction DAC.

Method and apparatus for quantization noise reduction in fractional-N PLLs

Efficient techniques improve the linearity of a charge pump in fractional-N PLLs. A feedback clock pulse several VCO clock periods wide is formed and supplied to a phase frequency detector (PFD). The down pulse generated by the PFD is fixed to eliminate the nonlinearity associated with up and down current source mismatch. The up pulse is made to fall when the down pulse falls, that is, when the feedback clock pulse falls.

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The present invention provides an alternative to Prior Art isolation techniques by providing a capacitively coupled reference voltage and a capacitively coupled gain calibration. The isolation technique of the present invention is based upon the idea of a near unity gain capacitive divider. If the load or parasitic capacitance is Cload and the isolation capacitance is Ciso, then the gain between input and output can be calculated as Vout/Vin&equals;(Ciso)/(Ciso&plus;Cload), which will be nearly unity (i.e., 1) when Ciso>>Cload. In addition, if Ciso>>Cload, the gain will also be largely insensitive to variations in Ciso and Cload. For example, if Cin is 100 ppm of Ciso, then a 10% variation in Ciso or Cload results in only a 10 ppm variation in the voltage gain.

Capacitively coupled references for isolated analog-to-digital converter systems

The present invention provides a method and apparatus to define and sustain such a physical level by connecting the output through a transmission gate to an input pin. For a certain state of the output, one level of an input may be fed through to the output to generate an output voltage level. In the preferred embodiment of the present invention, a chip select signal {overscore (CS)} is used to define a low level logic signal. An control logic selectively switches a high level logic signal voltage (e.g., V&plus;supply voltage) or the low level logic signal voltage ({overscore (CS)}) to produce an output digital logic signal. In a further embodiment of the present invention, separate logic level signals IN and IN may be selectively switched by control logic to generate an output logic level signal independent of supply voltages V&plus; and V&minus;.

Definition of physical level of a logic output by a logic input

An analog-to-digital converter (ADC) architecture is fabricated on a semiconductor substrate which is negatively capacitively charge pumped below ground and subject to feedback regulation, rate measurements and adjustments. The ADC receives signal inputs of positive and negative polarity relative to ground, while being powered at 0V and 5V, without any negative power source input, as a result of a closed feedback loop which keeps the negative bias voltage constant as external supplies and component voltages vary. The high frequency pumping of the silicon substrate is subject to timing requirements which permit high resolution analog input signals to be converted in the presence of pump noise.

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Lexington, MA, United States of America

Qicheng Yu