Xiamen Tianma Micro-electronics Co., Ltd.

Tianma Micro-electronics Co., Ltd.

Qiangcan Huang

Tao Peng

Bingping Liu

Min Huang

Xiai Xu

A touch display panel and a display device are provided. The touch display panel includes a display region and a non-display region. The display region includes a plurality of pixel electrodes and a plurality of touch control electrodes, and the non-display region includes a fan-out region and a bonding region used to bond a driving circuit. The bonding region includes a plurality of first pads and a plurality of second pads. A first pad is electrically connected to a signal output terminal of the driving circuit. A second pad is electrically connected to a signal input terminal of the driving circuit. The fan-out region includes a plurality of first trace wires electrically connected to the plurality of pixel electrodes as well as the plurality of first pads, and a plurality of second trace wires electrically connected to the touch control electrodes as well as the plurality of second pads.

Touch display panel and touch display device thereof

Embodiments of the present disclosure provide a pulse generation device, an array substrate, a drive circuit and a driving method. The pulse generation device includes: a reset module making a pulse output end output low level, in response to a low level of a first input end or in response to a low level of a second input end and a low level of a third input end; a pulse generation module making the pulse output end output a high level, in response to a high level of the first input end, a high level of the second input end and a low level of the third input end or in response to a high level of the first input end, a low level of the second input end and a high level of the third input end.

Pulse generation device, array substrate, display device, drive circuit and driving method

The present invention discloses a gate driving circuit and a display device having the same. The gate driving circuit includes a logic circuit, a plurality of shift register units and enable circuits. The logic circuit is configured to receive a first clock signal, a second clock signal, a third clock signal, and a fourth signal, and output a logic pulse signal for driving the plurality of shift register units and enable circuits. Each of the plurality of enable circuits is connected with one of the plurality of shift register units and configured to receive a first pulse signal outputted by one of the plurality of shift register units and the logic pulse signal outputted by the logic circuit, and output two second pulse signals to drive two respective gate lines.

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Xiamen, China

Qiangcan Huang