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Jiangyu Kangjian Innovation Medical Technology(chengdu) Co., Ltd

Sichuan Highway Planning, Survey, Design and Research Institute Ltd

Institute of Mountain Hazards and Environment, Cas

Chengdu Huawei Electronic Technology Co., Ltd.

Qiang Yu

Yuanjun Cen

Jinda Yang

Ying-Wei Sheng

Ping-Hao Liu

Peng Li

Wei-Chien Hsu

Chi-Fan Lin

Huayong Chen

Yu Lei

Yang Jia

Dong Wang

Yonggang Ge

Zhengbo Huang

Changfeng Liu

Jin-Jin Zou

Lu Sun

Huilong Pu

Yixin Wang

Shengfu Li

Junwen Peng

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The present disclosure relates to the field of early warning for geological disasters, and discloses an early warning method for icefall-caused moraine lake outburst disasters, which aims at solving the problems of low early warning precision and difficulty in implementation in an early warning solution of the prior art. The method includes: S1, calculating topographic parameters of moraine lakes and upstream glaciers thereof, and filtering a moraine lake to undertake focal monitoring; S2, calculating a freezing-thawing cycle index and a regional accumulated temperature index of an upstream glacier region for the moraine lake to undertake focal monitoring, S3, calculating a catastrophic climate determination factor T, wherein if the catastrophic climate determination factor Tsatisfies a corresponding catastrophic climate determination condition, an early warning condition is satisfied, otherwise the early warning condition is not satisfied; and S4, implementing early warning.

Early warning method for icefall-caused moraine lake outburst disasters

The disclosure belongs to the field of integrated circuits, and is used for reducing an area overhead and a power consumption of a pipelined analog-to-digital converter. Each stage of the pipelined analog-to-digital converter according to the disclosure comprises an analogue-to-digital converter, a digital-to-analog converter, a subtractor and an amplifier. According to the disclosure, an amplification time of the pipelined ADC is used for extra quantization, and a number of bits of each ADC is reduced on the premise of not increasing a number of stages of the pipelined ADC, so that a scale of each circuit is greatly reduced, and the power consumption and the area overhead are reduced.

Analogue-to-digital conversion method of pipelined analogue-to-digital converter and pipelined analogue-to-digital converter

Disclosed is a high-linearity low-voltage input buffer circuit. The buffer circuit includes main buffers of positive and negative input terminals comprised of NMOS transistor Mand Mas well as Mand M, auxiliary buffer comprised of PMOS transistors Mand Mas well as Mand M, replica current amplifier comprised of NMOS transistors Mand Mas well as Mand M. Two ends of a replica capacitor Cc are respectively connected with positive and negative output terminals of the auxiliary buffer. The auxiliary buffer is used to simulate a load effect of the main buffers to generate a replica current of a load current, then the replica current is mirrored to a load transistor of the main buffer by the current amplifier, and the load capacitor is charged and discharged through the load transistor.

High linearity and low voltage input buffer circuit

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Chengdu, China

Qiang Yu