Xilinx, Inc.

Apple Inc.

Qiang Wang

Jason Helge Anderson

Srinivasan Dasasathyan

Rajat Aggarwal

Subodh Gupta

Xin Ru Wang

Hao Pan

Sudip K Nag

Aaron Ng

Xiaohua Yang

Tetse Jang

Haiyan He

Kevin Chung

James L Saunders

Vaidyanath Mani

Pavanish Nirula

Ruiqi Hu

Gui Xie

A device comprises memory, a display characterized by a display characteristic, and processors coupled to the memory. The processors execute instructions causing the processors to receive data indicative of the display characteristic, data indicative of ambient lighting, and data indicative of content characteristics for a content item; determine a tone mapping curve for the content item based on the data indicative of content characteristics; determine a first, so-called 'anchor' point along the tone mapping curve; modify a first portion of the tone mapping curve below the anchor point based on the data indicative of ambient lighting; modify a second portion of the tone mapping curve above the anchor point based on the data indicative of the display characteristic; perform tone mapping for the content item based on the modified toned mapping curve to obtain a tone mapped content item; and cause the display to display the tone mapped content item.

Ambient headroom adaptation

A method of placing a circuit design in logic blocks of an integrated circuit is disclosed. The method comprises receiving a circuit design to be implemented in the logic blocks of the integrated circuit; determining clock skew for a clock tree providing clock signals to a plurality of memory elements of the integrated circuit; evaluating timing requirements associated with the circuit design; and transforming the circuit design to a placement configuration, wherein the placement configuration places the circuit design in the logic blocks of the integrated circuit according to the timing requirements of the circuit design and the clock skew for the clock tree.

Method of and system for generating a logic configuration for an integrated circuit

A method is provided whereby a placement-based cost function is utilized to minimize leakage and dynamic power that is consumed by clock networks implemented within integrated circuits (ICs) such as field programmable gate arrays (FPGAs). An initial placement of clock signal loads is analyzed to determine whether an alternative placement of clock signal loads results in the reduction of the usage of vertical clock spines, or equivalently, the optimization of the cost function. Several desirable characteristics are obtained through strategic clock signal load placement within the FPGA in accordance with the cost function. First, the number of clock regions spanned by a particular clock signal is minimized. Second, interconnect capacitance within the clock region is also minimized. By minimizing the total capacitance of a particular clock network implemented within a clock region, the leakage and dynamic power consumed by the clock network within the clock region is also minimized.

Method and apparatus for reducing clock signal power consumption within an integrated circuit

The availability of device resources of an IC are quantified for a circuit design by building a representation of resource sites for the IC. Initial availability values are assigned to the resource sites, and any components having locking constraints are identified and placed into their respective sites. From the remaining resource sites, candidate sites for a component of the circuit design are identified. The candidate sites are summed, and the initial availability values of the candidate sites are modified according to the sum.

Resource mapping of functional areas on an integrated circuit

Disclosed are processor-implemented methods for technology mapping a logic network onto programmable logic resources of a programmable logic device. The methods include determining respective Boolean flexibility values for a plurality of functionally equivalent mappings of the logic network onto the programmable logic resources, selecting one of the mappings as a function of the respective Boolean flexibility values, and storing the selected mapping.

Method for technology mapping considering boolean flexibility

Various approaches for generating an implementation of an electronic circuit design are disclosed. In one approach, one or more configuration bits that have don't care conditions are identified for a LUT block of a design. A dynamic power state for a subset of a first level of logic devices in the LUT block is determined as a function of each identified configuration bit that has a don't care condition. A dynamic power state for a subset of a second level of logic devices is determined as a function of the determined power state for the first level of logic devices. A respective value for each identified configuration bit of the LUT is selected in response to the determined dynamic power states. The respective value is placed into the design for each identified configuration bit.

Method and apparatus for power optimization using don't care conditions of configuration bits in lookup tables

A computer-implemented method of performing a Computer-Aided Design (CAD) flow on a circuit design for a programmable logic device (PLD) can include inserting a preprocessing task into the CAD flow prior to a selected task that does not recognize a constraint, wherein the preprocessing task introduces a modification into the circuit design according to the constraint. The circuit design including the modification can be processed through the selected task of the CAD flow. A reversal task can also be inserted into the CAD flow, wherein the reversal task removes the modification introduced into the circuit design by the preprocessing task. The method further can include processing the circuit design through at least one other task of the CAD flow and outputting the processed circuit design.

Processing constraints in computer-aided design for integrated circuits

A method () of placing local clock nets in a circuit design can include identifying the local clock nets for the circuit design and selecting components corresponding to each local clock net (), and assigning initial locations to each component of the local clock nets (). The method further can include generating at least one cost function () to evaluate () different placements of components of the local clock nets. The components () of the local clock nets () can be annealed () using one or more of the cost functions to assign locations to each component of the local clock nets.

Automated local clock placement for FPGA designs

A method () of placing inputs, outputs, and clocks in a circuit design can include assigning () initial locations to inputs and outputs of the circuit design, selecting () at least one component type for the circuit design, and generating () a cost function having parameters corresponding to the selected component type. The method further can include annealing () the selected component type using the cost function and determining design constraints () for the selected component type according to the annealing step. The method can repeat to process additional component types such that design constraints determined for each additional component type do not violate design constraints determined for prior component types.

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Campbell, CA, United States of America

Qiang Wang