Synopsys, Inc.

Atieva, Inc.

Qiang Lu

Victor Moroz

Tsu Jae King Liu

Stephen Lee Smith

Xi-Wei Lin

Terry Sylvan Kam-Chiu Ma

Hiu Yung Wong

Karim El Sayed

Tse Jae King Liu

A computer-implemented method comprises: generating first output using a first sensor of a vehicle comprising an infrared camera or an event-based sensor, the first output indicating a portion of surroundings of the vehicle; providing the first output to a LiDAR of the vehicle having a field of view (FOV); configuring a resolution of the LiDAR based at least in part on the first output; generating a representation of at least part of the surroundings of the vehicle using the LiDAR; providing, to a perception component of the vehicle, second output of a second sensor of the vehicle and third output of the LiDAR, the perception component configured to perform object detection, sensor fusion, and object tracking regarding the second and third outputs, wherein the first output bypasses at least part of the perception component; and performing motion control of the vehicle using a fourth output of the perception component.

Sensor-based control of LiDAR resolution configuration

A vehicle warning sign comprises: a reflective material for at least visible light; and at least one of (i) a heating element for detection by a thermal sensor or (ii) a corner reflector for detection by a radar, the corner reflector oriented substantially in a common direction with the reflective material.

Sensor-friendly vehicle warning sign

Roughly described, a computer program product describes a transistor with a fin, a fin support, a gate, and a gate dielectric. The fin includes a first crystalline semiconductor material which includes a channel region of the transistor between a source region of the first transistor and a drain region of the transistor. The fin is on a fin support. The fin support includes a second crystalline semiconductor material different from the first crystalline semiconductor material. The first crystalline semiconductor material of the fin and the second crystalline semiconductor material of the fin support form a first heterojunction in between. A gate, gate dielectric, and/or isolation dielectric can be positioned to improve control within the channel.

FinFET with heterojunction and improved channel control

The independent claims of this patent signify a concise description of the embodiments. Disclosed is technology for reducing transistor degradations by annealing through heat generated by anti-punch-through implants of the transistors. A first and second electrically conductive pillars are disposed on top a well hosting the transistors. A voltage applied across the first and second pillars enable the anti-punch-through implants to generate heat for the annealing process.

On-chip heating and self-annealing in FinFETs with anti-punch-through implants

Roughly described, a method for developing a set of design rules for a fabrication process in development includes, for each of several candidate DRUTs for the fabrication process, laying our a logic cell based on the DRUT, the logic cell having at least one transistor and at least one interconnect, simulating fabrication of the logic cell according to the fabrication process and the layout, simulating behavior of the logic cell structure, including characterizing the combined behavior of both the first transistor and the first interconnect, evaluating performance of the logic cell structure in dependence upon the behavior as characterized, and recording in a database, in association with an indication of the DRUT, values indicating performance of the logic cell. The database can be used to select the best DRUT for the fabrication process.

Pre-silicon design rule evaluation

FinFet with heterojunction and improved channel control

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a 'corrugated substrate'), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably produced. Ridges on the corrugated substrate can be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping, 'wrapped' gates, epitaxially grown conductive regions, epitaxially grown high mobility semiconductor materials, high-permittivity ridge isolation material, and narrowed base regions can be used in conjunction with the segmented channel regions to further enhance device performance.

Enhanced segmented channel MOS transistor with multi layer regions

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a 'corrugated substrate'), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. A multi step epitaxial process can be used to extend the ridges with different dopant types, high mobility semiconductor, and or advanced multi-layer strutures. For CMOS integrated circuits a capping layer is formed over the a first region. Epitaxial layers are formed in a second region. Then the capping layer is removed from the first region and a capping layer is formed over the second region. Epitaxial layers can than be formed in the first region.

Sequential selective epitaxial growth

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a 'corrugated substrate'), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping, 'wrapped' gates, epitaxially grown conductive regions, epitaxially grown high mobility semiconductor materials (e.g. silicon-germanium, germanium, gallium arsenide, etc.), high-permittivity ridge isolation material, and narrowed base regions can be used in conjunction with the segmented channel regions to further enhance device performance.

Growing community of inventors

Foster City, CA, United States of America

Qiang Lu