Rambus Inc.

Qiang Hong

Paul Wong

Kevin D Jones

Thomas J Sheffler

Kathryn M Mossawir

Jing Jiang

Data structures and algorithms are provided to automatically generate an analog stimulus to apply to a simulation of the analog DUT. A constraint solver is provided to determine suitable values to use in the stimulus generation. The suitable values are random values within a range of allowed values. For example, a number of different stimuli are generated for successive application to the analog DUT, each with a different magnitude within a range of allowed magnitudes. Data structures and algorithms are provided to monitor analog electrical properties at nodes of the analog DUT. Data structures and algorithms are provided to define constraints on the analog electrical properties and determine whether the constraints were violated. Data structures and algorithms are provided to define simulation coverage conditions in the analog domain and determine whether the defined analog domain coverage conditions have been satisfied.

Method to analyze an analog circuit design with a verification program

A method and system for performing consistency checking of one or more design representations having different design types. A translator for each design type obtains information from each design needed to evaluate rules that are design type-neutral. The described examples also allow a user to add rules using predefined rule terms. In addition, certain examples allow the user to add terms to the rule set and to make new rules with the added terms. Each new term added to a rule set has a corresponding abstraction function in a translator for each design type. Thus, the abstraction functions are not design type-neutral.

Multi-format consistency checking tool

A method and system for formally verifying designs having elements from more than a single design domain is described. An example system allows formal verification of a design containing mixed analog and digital subparts. The system may use different proof engines to solve an appropriate sub-partition of the entire design, and may provide a framework for translating between the different domains to create a unified result. For example, a digital proof engine may be used for a digital only subpart, while an analog proof engine may be used for an analog only subpart. The system may use the partitioning results to determine translators between the various domains, and an order in which the proof engines are applied.

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San Jose, CA, United States of America

Qiang Hong