Micron Technology Incorporated

Intel Corporation

Wuxi Petabyte Technologies Co, Ltd.

Qian Tao

Durai Vishak Nirmal Ramaswamy

Ashonita A Chavan

Matthew N Rocklein

Haitao Liu

Kirk D Prall

Kamal M Karda

Beth R Cook

Yongjun Jeff Hu

Everett Allen McTeer

David A Daycock

Noel Rocklein

Christopher J Larsen

Tsz Wah Chan

John David Hopkins

Scott E Sills

Shuichiro Yasuda

Barbara L Casey

Justin B Dorhout

Richard J Hill

Brett D Lowe

Zhe Song

Woohee Kim

Christopher W Petz

Sanket S Kelkar

Roy Edward Meade

Vishwanath Bhat

Yushi Hu

Vassil N Antonov

Sumeet C Pandey

Zhenyu Lu

Purnima Narayanan

Lei Bi

Meng-Wei Kuo

Paul A Paduano

Rithu K Bhonsle

Srivardhan Gowda

Devesh Kumar Datta

Saniya Rathod

Guoxing Duan

D V Nirmal Ramaswamy

DV Nirmal Ramaswamy

A DRAM capacitor comprising a first capacitor electrode configured as a container and comprising a doped titanium nitride material, a capacitor dielectric on the first capacitor electrode, and a second capacitor electrode on the capacitor dielectric. Methods of forming the DRAM capacitor are also disclosed, as are semiconductor devices and systems comprising such DRAM capacitors.

Doped titanium nitride materials for dram capacitors, and related semiconductor devices

A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.

Semiconductor devices including ferroelectric materials

A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

Memory cells

A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.

Semiconductor devices comprising threshold switching materials

Doped titanium nitride materials for DRAM capacitors, and related semiconductor devices, systems, and methods

Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.

Memory cells and methods of forming memory cells

Methods of forming memory cells and memory devices

A 3D NAND storage device includes a plurality of layers containing doped semiconductor material interleaved with a plurality of layers of dielectric material. Each of the pillars forming the 3D NAND storage device includes a plurality of memory cells and a drain-end select gate (SGD). The pillars are separated by a hollow channel in which a plurality of film layers, including at least a lower film layer and an upper film layer have been deposited. The systems and methods described herein remove at least the upper film layer proximate the SGD while maintaining the film layers proximate the memory cells. Such an arrangement beneficially permits tailoring the film layers proximate the SGD prior to depositing the channel film layer in the hollow channel. The systems and methods described herein permit the deposition of a continuous channel film layer proximate both the memory cells and the SGD.

3D NAND with integral drain-end select gate (SGD)

Computer memory technology is disclosed. In one example, a method for isolating computer memory blocks in a memory array from one another can include forming an opening between adjacent blocks of memory structures. The method can also include forming a protective liner layer on at least the memory structures. The method can further include disposing isolating material in the opening and on the protective liner layer. The method can even further include removing the isolating material on the protective liner layer. The method can additionally include removing the protective liner layer on the memory structures. Associated devices and systems are also disclosed.

Computer memory

Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

Memory arrays, and methods of forming memory arrays

Methods of forming memory cells and semiconductor devices

Growing community of inventors

Boise, ID, United States of America

Qian Tao